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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Yu Yang Chen Yefu Peng Yu |
| Copyright Year | 2011 |
| Description | Author affiliation: Dept. of Automatic Test and Control, Harbin Institute of Technology, Heilongjinag 150001, China (Yu Yang; Chen Yefu; Peng Yu) |
| Abstract | Recently, system-on-a-Programmable-Chip (SOPC) has become more and more popular. However, prior research only concentrated on System on Chip (SoC) test problem. In this paper, we address the SOPC test problem. An SOPC test strategy has been proposed to solve the wrapper/TAM co-optimization problem for the SOPC. Our wrapper design algorithm is proposed on earlier approach by arranging the internal scan chains scientifically to archive lower testing time. Then we present a new test schedule technique, in which the testing time for each IP cores are calculated by our wrapper design algorithm. Experimental results are present for ITC'02 test benchmark as well as Integrated Processor. |
| Starting Page | 331 |
| Ending Page | 335 |
| File Size | 180722 |
| Page Count | 5 |
| File Format | |
| ISBN | 9781424481583 |
| e-ISBN | 9781424481613 |
| DOI | 10.1109/ICEMI.2011.6037828 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-08-16 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Schedules test schedule SOPC Pins IP networks System-on-a-chip wrapper design Hardware design languages Field programmable gate arrays Testing |
| Content Type | Text |
| Resource Type | Article |
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