NDLI: High-speed FPGA-based SOPC application for currency sorting system

Content Provider	IEEE Xplore Digital Library
Author	Wu Jianping Ye Yutang Liu Lin Huang Bingquan Guo Tao
Copyright Year	2011
Description	Author affiliation: College of Optoelectronic Information, University of Electronic Science and Technology of China, Chengdu 610054, China (Wu Jianping; Ye Yutang; Liu Lin; Huang Bingquan; Guo Tao)
Abstract	A high-speed real-time currency sorting system based on SOPC of FPGA is designed against the existing problems in our country, such as the high complexity, the lower stability, the low real-time performance of complex algorithms for high-speed digital image signal and that the system is difficult to upgrade in real time, etc. The methods of software simulation, real-time debugging online are applied; the real-time processing of complex image algorithms has been achieved successfully and the system complexity has been reduced; the integration and stability of the system have been greatly improved. Furthermore the operation of FPGA could be performed in parallel and the responsive time of its hardware could be accurate to nanosecond (ns) level. So the real-time processing properties of the system have more advantages against other processing platforms. Because of the system programmable performance, the real-time updates of the system without changing the hardware circuit have also been implemented.
Starting Page	85
Ending Page	89
File Size	313260
Page Count	5
File Format	PDF
ISBN	9781424481583
e-ISBN	9781424481613
DOI	10.1109/ICEMI.2011.6037771
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-08-16
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Real time systems currency sorting FPGA Debugging Educational institutions SOPC Hardware Software SDRAM Field programmable gate arrays MicroBlaze
Content Type	Text
Resource Type	Article

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