NDLI: Beyond UVM for practical SoC verification

Content Provider	IEEE Xplore Digital Library
Author	Young-Nam Yun Jae-Beom Kim Nam-Do Kim Byeong Min
Copyright Year	2011
Description	Author affiliation: Infrastructure Design Center, Samsung Electronics Co. Ltd., Yongin-City, Korea (Young-Nam Yun; Jae-Beom Kim; Nam-Do Kim; Byeong Min)
Abstract	As the size and complexity of SoC design grow, an efficient and structured verification environment is becoming more important than ever before. It is because many engineers with different knowledge and skills are involved in SoC verification, and they have to deal with different aspects of verification. This paper looks over the diversity of SoC verification and suggests a practical application method of UVM (Universal Verification Methodology) to build an efficient and structured verification environment which meets various requirements of SoC verification. This paper shows standardized and well-organized testbench architecture that includes directory structure of testbench files, and mechanism such as interface and handles across the components. The proposed UVM application method helps testbench developers maintain consistency of testbenches and reduce the quality gap among verification works that are done by multiple verification engineers, by using standardized testbench. It ensures that IP verification engineers do their job independently and the testbenches can be reused in top level verification environment. In addition, it provides a good infrastructure to hardware designers, who have little knowledge about verification languages and methodologies, and who want to write directed test cases only. The proposed method has been validated with a set of reference testbenches developed for an application processor SoC.
Starting Page	158
Ending Page	162
File Size	1971396
Page Count	5
File Format	PDF
ISBN	9781457707094
e-ISBN	9781457707117
e-ISBN	9781457707100
DOI	10.1109/ISOCC.2011.6138671
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-11-17
Publisher Place	Korea (South)
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	SystemVerilog testbench SoC Verification UVM
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

How to automate millions lines of top-level UVM testbench and handle huge register classes

How easier to built Basic Verification Testbench using UVM compared to SystemVerilog

Practical and efficient SOC verification flow by reusing IP testcase and testbench

Vmming a systemverilog testbench by example.

Case study on Universal Verification Methodology(UVM) SystemC testbench for RTL verification

The system verification methodology for advanced TLM verification

World class verilog, systemverilog & ovm/uvm training the ovm/uvm factory & factory overrides how they work- why they are important.

SystemVerilog-based verification environment using SystemC custom hierarchical channel

UVM based testbench architecture for unit verification

Beyond UVM for practical SoC verification

Similar Documents

How to automate millions lines of top-level UVM testbench and handle huge register classes

How easier to built Basic Verification Testbench using UVM compared to SystemVerilog

Practical and efficient SOC verification flow by reusing IP testcase and testbench

Vmming a systemverilog testbench by example.

Case study on Universal Verification Methodology(UVM) SystemC testbench for RTL verification

The system verification methodology for advanced TLM verification

World class verilog, systemverilog & ovm/uvm training the ovm/uvm factory & factory overrides how they work- why they are important.

SystemVerilog-based verification environment using SystemC custom hierarchical channel

UVM based testbench architecture for unit verification

Beyond UVM for practical SoC verification