NDLI: MTJ based non-volatile flip-flop in deep submicron technology

Content Provider	IEEE Xplore Digital Library
Author	Youngdon Jung Jisu Kim Kyungho Ryu Seong-Ook Jung Jung Pill Kim Kang, S.H.
Copyright Year	2011
Description	Author affiliation: Qualcomm Inc. San Diego, USA (Jung Pill Kim; Kang, S.H.) \|\| Dept. of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea (Youngdon Jung; Jisu Kim; Kyungho Ryu; Seong-Ook Jung)
Abstract	The NVFF (Non-Volatile Flip-flop) using a MTJ is one of the powerful solutions for the low power system. However, the previous NVFF cannot provide a sufficient current to write the data into the MTJ in deep submicron technology. This problem occurs due to the lowered supply voltage (1.1V for core device in 45nm technology) with technology scaling. It can be resolved by increasing the supply voltage. However, the increased supply voltage causes a reliability problem of the core device. In order to overcome this problem, the proposed write circuit adopts an IO device with an IO supply voltage of 1.8V. In addition, the low-skewed NAND (LS-NAND) is used to efficiently interface the two supply voltage levels of 1.1V and 1.8V and to minimize the short circuit current in the write circuit. In this paper, the NVFF with the proposed write circuit is verified by HSPICE simulation using an industry compatible 45nm model parameter. The write current of the proposed write circuit is 60% greater than that of the previous write circuit and is sufficient for the proper write operation.
Starting Page	424
Ending Page	427
File Size	875394
Page Count	4
File Format	PDF
ISBN	9781457707094
e-ISBN	9781457707117
e-ISBN	9781457707100
DOI	10.1109/ISOCC.2011.6138622
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-11-17
Publisher Place	Korea (South)
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Non-volatile flip-flop write current MTJ leakage current
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Spin-MTJ based Non-volatile Flip-Flop

Ferroelectric Transistor based Non-Volatile Flip-Flop

A Magnetic Tunnel Junction Based Zero Standby Leakage Current Retention Flip-Flop

A novel non-volatile flip-flop using a ferroelectric capacitor

Skewed flip-flop transformation for minimizing leakage in sequential circuits

Design of a Low Power Flip-Flop Using CMOS Deep Sub Micron Technology

OxRAM-based non volatile flip-flop in 28nm FDSOI

A true single-phase clocked flip-flop with leakage current compensation

A 2.4 pJ ferroelectric-based non-volatile flip-flop with 10-year data retention capability

MTJ based non-volatile flip-flop in deep submicron technology

Similar Documents

Spin-MTJ based Non-volatile Flip-Flop

Ferroelectric Transistor based Non-Volatile Flip-Flop

A Magnetic Tunnel Junction Based Zero Standby Leakage Current Retention Flip-Flop

A novel non-volatile flip-flop using a ferroelectric capacitor

Skewed flip-flop transformation for minimizing leakage in sequential circuits

Design of a Low Power Flip-Flop Using CMOS Deep Sub Micron Technology

OxRAM-based non volatile flip-flop in 28nm FDSOI

A true single-phase clocked flip-flop with leakage current compensation

A 2.4 pJ ferroelectric-based non-volatile flip-flop with 10-year data retention capability

MTJ based non-volatile flip-flop in deep submicron technology