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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Pei-Kuei Tsung Li-Fu Ding Wei-Yin Chen Tzu-Der Chuang Shao-Yi Chien Liang-Gee Chen |
| Copyright Year | 2010 |
| Description | Author affiliation: DSP/IC Design Lab, Graduated Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan (Pei-Kuei Tsung; Li-Fu Ding; Wei-Yin Chen; Tzu-Der Chuang; Shao-Yi Chien; Liang-Gee Chen) |
| Abstract | In recent years, 3D related applications, including 3D movie and 3DTV, are getting more and more attentions. In order to make the real-time 3D applications feasible, efficient multview video coding (MVC) scheme is desired. However, the system throughput requirement on a high definition (HD) MVC encoder is at least two times higher than the current highest throughput H.264/AVC encoder design. In order to meet the target HD MVC specifications, the system scheduling analysis for the HD MVC encoder is performed in this paper. By the 8-stage MB pipeline system architecture with view-parallel MB-interleaved system scheduling and other in-core computation optimizations, the proposed HD MVC encoder design provides about 339% to 1536% higher system throughput than the previous HD H.264/AVC encoder chips[4][5][6] and therefore the real-time HD MVC encoding can be achieved. |
| Starting Page | 87 |
| Ending Page | 90 |
| File Size | 275434 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424486335 |
| e-ISBN | 9781424486328 |
| DOI | 10.1109/SOCDC.2010.5682965 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-11-22 |
| Publisher Place | Korea (South) |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Prefetching Pipelines Throughput Encoding Automatic voltage control High definition video Optimization |
| Content Type | Text |
| Resource Type | Article |
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