NDLI: A sync processor with noise robustness for 3DTV active shutter glasses

Content Provider	IEEE Xplore Digital Library
Author	Daejin Park Tag Gon Kim Changmin Kim Sungho Kwak
Copyright Year	2010
Description	Author affiliation: Next Generation Business Unit, ABOV Semiconductor Co., Daechi-dong, Kangnam-gu, Seoul, Repblic of Korea (Changmin Kim; Sungho Kwak) \|\| Systems Modeling Simulation Lab, Dept. of EECS, Korea Advanced Institute of Science and, Technology (KAIST), 373-1, Guseong-dong, Yuseong-gu, Daejeon, 305-701, Republic of Korea (Daejin Park; Tag Gon Kim)
Abstract	A noise robust sync processor chip for 3DTV shutter glasses is proposed and implemented. The existing 3DTV shutter glasses have to receive the sync pulse continuously from the 3DTV to synchronize between two independently-clocked systems. These sync packets are easily interfered by the noise of fluorescent light and the existing TV remote controller signal. Especially the 3DTV users easily suffer from the flicker effect by the synchronization loss. The proposed sync processor adopts the CRC protection for the non-valid sync packet, frame indexing for the valid signal, and newly designed timer to synchronize without any sync signal reception for about one hour to achieve perfect noise robustness. The 3DTV shutter glasses controller including the proposed sync processor is fabricated in 0.18um CMOS technology, has a die size of 2.4mm × 2.3mm.
Starting Page	147
Ending Page	149
File Size	356644
Page Count	3
File Format	PDF
ISBN	9781424486335
e-ISBN	9781424486328
DOI	10.1109/SOCDC.2010.5682952
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-11-22
Publisher Place	Korea (South)
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	independently clocked digital subsystems Noise Glass Receivers digital systems design synchronization failure Three dimensional displays Noise robustness Stereo vision Synchronization Indexes
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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