NDLI: Timing issues for an efficient use of concurrent error detection codes

Content Provider	IEEE Xplore Digital Library
Author	Bastos, R.P. Di Natale, G. Flottes, M.L. Rouzeyre, B.
Copyright Year	2011
Description	Author affiliation: LIRMM (Université Montpellier II / CNRS UMR 5506), Montpellier, France (Bastos, R.P.; Di Natale, G.; Flottes, M.L.; Rouzeyre, B.)
Abstract	This work reveals additional timing difficulties by which concurrent error detection (CED) schemes can experience to deal efficiently with transients. It shows previously-unknown error scenarios where short-duration single transient faults in logic circuits succeed in erroneously inverting stored results but CED schemes fail in detecting even single soft errors. The paper demonstrates that typical CED code-based schemes for protecting logic circuits are not as capable as they have been claimed, and so timing conditions are suggested for a more efficient use of them.
Starting Page	1
Ending Page	6
File Size	505376
Page Count	6
File Format	PDF
ISBN	9781457714894
e-ISBN	9781457714900
DOI	10.1109/LATW.2011.5985933
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-03-27
Publisher Place	Brazil
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	fault attacks fault tolerance Registers Circuit faults Security transient faults concurrent error dectection codes security Fault tolerant systems Timing soft errors Transient analysis Clocks
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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Timing issues for an efficient use of concurrent error detection codes