NDLI: Reliability enhancement via Sleep Transistors

Content Provider	IEEE Xplore Digital Library
Author	Torres, F.S. Cornelius, C. Timmermann, D.
Copyright Year	2011
Description	Author affiliation: Inst. of Applied Microelectronics and Computer Engineering, University of Rostock, Germany (Cornelius, C.; Timmermann, D.) \|\| Department of Electronic Engineering, Federal University of Minas Gerais, Belo Horizonte, Brazil (Torres, F.S.)
Abstract	CMOS is still the predominating technology for digital designs with no identifiable concurrence in the near future. Driving forces of this leadership are the high miniaturization capability and the reliability of CMOS. The latter, though, is decreasing with an alarming pace against the background of technologies with sizes at the nanoscale. The consequence is a rising demand of solutions to improve lifetime reliability and yield of today's integrated systems. Thereby, a common solution is the redundant implementation of components. However, redundancy collides with another major issue of integrated circuits — power dissipation. The main contribution of this work is an approach that increases the lifetime reliability at only low delay and power penalty. Therefore, the well-known standby-leakage reduction technique “Sleep Transistors” is combined with the idea of redundancy. Additional, we propose an extended flow for reliability verification on transistor level. Simulation results indicate that the new approach can increase the lifetime reliability by more than factor 2 compared to initial designs.
Starting Page	1
Ending Page	6
File Size	314951
Page Count	6
File Format	PDF
ISBN	9781457714894
e-ISBN	9781457714900
DOI	10.1109/LATW.2011.5985901
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-03-27
Publisher Place	Brazil
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Multiplexing Electromigration simulation Logic gates redundancy Transistors Integrated circuit reliability reliabiltiy Switching circuits sleep transistors
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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