NDLI: Theoretical performance of a GPS linked Pulsed Ring Down Array

Content Provider	IEEE Xplore Digital Library
Author	Reale, D. Mankowski, J. Holt, S. Chen, Y. Walter, J. Dickens, J.
Copyright Year	2010
Description	Author affiliation: Center for Pulsed Power and Power Electronics, Department of Electrical and Computer Engineering, Texas Tech University, Lubbock, TX 79409 (Reale, D.; Mankowski, J.; Holt, S.; Chen, Y.; Walter, J.; Dickens, J.)
Abstract	Current research at Texas Tech University is focused on the development of a High-Power Pulsed Ring-Down Source (PRDS) Antenna Array. Previously, a Monte Carlo based analysis was conducted in order to predict the array performance based upon the estimated switching jitter between elements [1]. This analysis showed good performance for jitter times between 0 to 2 periods of the ringing frequency. Therefore, for ringing frequencies up to 500 MHz, jitter times up to 4 nanoseconds can be tolerated. Subsequently, we have shown practical switching solutions capable of the sub-nanosecond switching performance needed for the frequencies of interest [2]. Taking the analysis a step further, we introduce the uncertainty of the absolute position of each antenna element. To implement a randomly distributed array, where the position of elements is not fixed, a method of accurately resolving element positions relative to each other and the target location is required. The use of a variety of GPS technologies and techniques is explored as a method for position and timing resolution. The relative accuracy between elements and the absolute accuracy of each element is discussed. A Monte Carlo based analysis is conducted to predict array performance based upon GPS positional error, GPS timing error, and switch jitter.
Starting Page	628
Ending Page	631
File Size	834629
Page Count	4
File Format	PDF
ISBN	9781424471317
ISSN	1930885X
e-ISBN	9781424471324
DOI	10.1109/IPMHVC.2010.5958437
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-05-23
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Accuracy Switches Jitter Timing Arrays Electric fields Global Positioning System
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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