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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Kato, Takuya Yamamoto, Shintaro Sudo, Toshio Ono, Yasushi Takahashi, Eiji Yamada, Toru |
| Copyright Year | 2011 |
| Description | Author affiliation: PE & EMC Technology Dev. Office, Panasonic Corp., 1006 Kadoma, Osaka 571-8501, Japan (Ono, Yasushi; Takahashi, Eiji; Yamada, Toru) || Dept. of Electronic Engineering, Shibaura Institute of Technology, Toyosu 3-7-5, Koto-ku, Tokyo, Japan (Kato, Takuya; Yamamoto, Shintaro; Sudo, Toshio) |
| Abstract | With the increase of the clock speed of memory systems, signal integrity is becoming more an important design issue to ensure system reliability. DDR2 memory systems adopt on-die termination scheme to reduce reflection noise on a transmission lines. This paper describes a correct prediction method of waveforms at the receiver chip from the waveforms at the vicinity of the packaged chip. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 1042015 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781467322881 |
| ISSN | 21511233 |
| e-ISBN | 9781467322904 |
| e-ISBN | 9781467322898 |
| DOI | 10.1109/EDAPS.2011.6213776 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-12-12 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | DDR2 memory Power transmission lines signal integrity TDR Receivers Predictive models Transmission line measurements SPICE Impedance Monitoring S parameter |
| Content Type | Text |
| Resource Type | Article |
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