NDLI: An IEEE Compliant Floating-Point Adder with the Deeply Pipelining Paradigm on FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Shao Jie Ye Ning Zhang Xiao-Yan
Copyright Year	2008
Description	Author affiliation: Dept. of Inf. Sci., Nanjing Coll. for Population, Nanjing (Ye Ning) \|\| Coll. of Inf. Sci. & Technol., Nanjing Univ. of Aeronaut. & Astronaut., Nanjing (Shao Jie; Zhang Xiao-Yan)
Abstract	FPGAs are increasingly being used to design high-end computationally intense microprocessors capable of implementing floating-point operations based hardware accelerators. In this paper, the throughput was improved by increasing the number of pipelining stages of the floating-point adder, and the feasibility of advancing the system clock rate was researched by making the most of plenty of flip-flops in FPGAs. The multi-paths floating-point adder/subtractor architecture that was the separate exponents/mantissas operations and the separate addition/subtraction datapaths was presented. On Alterapsilas Stratix II series FPGA, we achieved throughput rates more than 375 MHz (329 MHz) for single (double) precision operations by 8(12)-stages deeply pipelining units.
Starting Page	50
Ending Page	53
File Size	323491
Page Count	4
File Format	PDF
ISBN	9780769533360
DOI	10.1109/CSSE.2008.590
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-12-12
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Multiplexing FPGA Throughput Educational institutions Delay Pipeline processing Information science Floating-point adder Signal processing algorithms Pipelining Logic Field programmable gate arrays Clocks
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in