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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Yamamoto, T. Hasegawa, K. Ishida, M. Takao, K. |
| Copyright Year | 2014 |
| Description | Author affiliation: Corp. Manuf. Eng. Center, Toshiba Corp., Yokohama, Japan (Yamamoto, T.; Hasegawa, K.; Ishida, M.) || Corp. R&D Center, Toshiba Corp., Kawasaki, Japan (Takao, K.) |
| Abstract | In this paper, we present a simulation technique for a high-power module using silicon carbide (SiC) phase leg units. Each phase leg unit has parasitic inductances that are caused by bonding wires and patterns on a substrate in the phase leg unit. The parasitic inductances are extracted using a quasi-electromagnetic simulation tool. We also estimate mutual inductances between the parasitic inductances in the high-power module. We fabricate a high-power module that consists of six phase leg units with low parasitic inductance. Simulation results show a spike voltage of 156 V and a total parasitic inductance of 7.1 nH. Measurement results indicate a spike voltage of 154 V and a total parasitic inductance of 8.1 nH. These results show that the proposed technique is appropriate for predicting the switching performances of the high-power modules. |
| Starting Page | 3707 |
| Ending Page | 3711 |
| File Size | 1642203 |
| Page Count | 5 |
| File Format | |
| ISBN | 9781479927050 |
| ISSN | 21506086 |
| DOI | 10.1109/IPEC.2014.6870031 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-05-18 |
| Publisher Place | Japan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Integrated circuits Silicon carbide parastic inductance Capacitance-voltage characteristics Silicon carbide (SiC) devices Field effect transistors simulation power modules Logic gates Electromagnetic compatibility Switching circuits |
| Content Type | Text |
| Resource Type | Article |
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