NDLI: Frame and arithmetic pipelining for a radix-4 FFT streamed core

Content Provider	IEEE Xplore Digital Library
Author	Rodríguez, J.A. Julián, P.M. Andreou, A.G.
Copyright Year	2010
Description	Author affiliation: Departamento de Ingenier?a El?ctrica y Computadoras, and Instituto de Investigaciones en Ingenier?a El?ctrica, Universidad Nacional del Sur/CONICET, Av. Alem 1253, (8000) Bah?a Blanca, Argentina (Rodríguez, J.A.; Julián, P.M.) \|\| Electrical Engineering Department, Johns Hopkins University, 3400 North Av., (21218) Baltimore, USA (Andreou, A.G.)
Abstract	This work presents the architecture of a pipelined 512 point radix 4?2 Fast Fourier Transform (FFT) core. Two pipelining dimensions were specified. The frame pipeline manages the data frames (input, current and output) and ensures a continuous-flow maintaining input/output transactions and the FFT evaluation without any stalls. The arithmetic pipeline was optimized by an iterative logic synthesis study down with Design Compiler to push the clock frequency to 1 GHz. This under-development FFT core was implemented with Hardware Description Language (HDL) and logically and physically synthesized with standard Electronic Design Automation (EDA) tools for a 130 nm process.
Starting Page	112
Ending Page	116
File Size	850670
Page Count	5
File Format	PDF
ISBN	9781424467471
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-10-01
Publisher Place	Uruguay
Access Restriction	Subscribed
Rights Holder	EdiUNS
Subject Keyword	Algorithm design and analysis Microprocessor Architecture VLSI Discrete Fourier transforms Signal processing algorithms Computer architecture Fast Fourier Transform Logic Synthesis Registers Pipeline processing Clocks
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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