NDLI: An ultra-low power CMOS PTAT current source

Content Provider	IEEE Xplore Digital Library
Author	Christoffersen, C. Toombs, G. Manzak, A.
Copyright Year	2010
Description	Author affiliation: Department of Electrical and Computer Engineering, University of Windsor, Windsor, ON N9B 3P4, Canada (Toombs, G.) \|\| Department of Electrical Engineering, Lakehead University, Thunder Bay, ON P7B 5E1, Canada (Christoffersen, C.; Manzak, A.)
Abstract	A low-voltage, ultra-low-power sub-threshold proportional to absolute temperature (PTAT) current source is proposed. The new topology generates the PTAT current from the ratio between the drain currents of two transistors in subthreshold operation. Linearity is analyzed and a compensation strategy to improve it is developed. This is the first time such a design scheme is presented. Total current drain for the circuit is approximately 3.8 ?A with a minimum supply voltage of 1 V and a PSRR greater than 50 dB at room temperature. The linear range is at least from ?40 ?C to 125 ?C. The performance of the proposed reference is compared with several existing designs.
Starting Page	35
Ending Page	40
File Size	787486
Page Count	6
File Format	PDF
ISBN	9781424467471
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-10-01
Publisher Place	Uruguay
Access Restriction	Subscribed
Rights Holder	EdiUNS
Subject Keyword	Resistors Linearity Logic gates Sensors Transistors Mirrors Gain
Content Type	Text
Resource Type	Article

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An ultra-low power CMOS PTAT current source