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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Dongxing Bao Xiaoming Li |
| Copyright Year | 2010 |
| Description | Author affiliation: Microelectronic Center, Harbin Institute of Technology, Heilongjiang, China (Xiaoming Li) || College of Electronic Engineering, Heilongjiang University, Harbin, China (Dongxing Bao) |
| Abstract | The LRU-like algorithm was proposed for the block management to enhance the direct-mapped cache scheme. Base on the LRU-like algorithm, the Least-Recently-Used Block Filtering cache (LBF cache), which can filter LRU blocks, is designed. From the point of cache usage rate, the LBF cache uses LRU-like algorithm to allocate and replace blocks, and evicts the blocks whose usage shows the least efficiency. After the simulation, the performance of LBF cache shows better performance than typical cache schemes with similar architecture (such as victim cache and assist cache). Comparison also shows, with the same block size of 32 bytes, 9KB LBF cache reduces 26% in average miss rate over the traditional 16KB direct-mapped cache and 53% over the 8KB 2-way set-associative cache. |
| Starting Page | 2055 |
| Ending Page | 2060 |
| File Size | 104568 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424457014 |
| e-ISBN | 9781424457045 |
| DOI | 10.1109/ICINFA.2010.5512483 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-06-20 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Automation miss rate LRU algorithm Conference management Educational institutions Delay Filters Microprocessors Engineering management Filtering algorithms Hardware Delta modulation Cache |
| Content Type | Text |
| Resource Type | Article |
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