NDLI: Underfill encapsulant technology for flip chip assembly

Content Provider	IEEE Xplore Digital Library
Author	Gilleo, K. Nicholls, G. Ongley, P.E.
Copyright Year	1997
Description	Author affiliation: Alpha APD, USA (Gilleo, K.)
Abstract	Direct chip attach (DCA) flip chip assembly offers many advantages in terms of signal speed and performance, compactness, weight and long term cost savings. The growth of portable electronics has focused attention on the use of flip chip attach, where all of these virtues are attractive. Selection of uniquely compatible materials for advanced assembly and packaging is rarely possible and a compromise is nearly always needed. This is particularly the case with DCA of complex Si devices using bumped technology for interconnection and mechanical attachment to the substrate. While there is considerable interest in the use of specialised conductive polymer adhesives, the implementation of DCA mainly relies on metallurgical connection between chip and substrate pad, whether it be the C4 solder bump process or the recent Au stud technique. The inevitable CTE mismatch between chip and composite substrate must be managed for long term joint reliability. Early work in DCA/flip chip development has shown clearly the possibility of joint dislocation and failure when the device is thermally stressed, particularly under extended rapid temperature cycling. Polymer-based underfill encapsulant materials have been developed and formulated to minimise the effect of /spl Delta/CTE induced stresses which manage the problem effectively by acting as a mechanical compensator layer between chip and substrate. This paper outlines the basic requirements of the underfill material, the effects of CTE mismatch and methods of application. An overview of typical problems with flip chip/underfill encapsulants is also presented.
Starting Page	315
Ending Page	325
File Size	603655
Page Count	11
File Format	PDF
ISBN	0780338650
DOI	10.1109/PEP.1997.656505
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-10-30
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Gold Costs Rapid thermal processing Temperature Flip chip Polymers Conducting materials Assembly Thermal stresses Electronics packaging
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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