NDLI: Implementation of a bit-level super-systolic FIR filter

Content Provider	IEEE Xplore Digital Library
Author	Jae-Jin Lee Gi-Yong Song
Copyright Year	2004
Description	Author affiliation: Sch. of Electr. & Comput. Eng., Chung-Buk Nat. Univ., Cheongju, South Korea (Jae-Jin Lee; Gi-Yong Song)
Abstract	High performance computation on a large array of cells has been an important feature of the systolic array. To achieve higher degree of concurrency, it is desirable to make cells of a systolic array themselves a systolic array as well. The structure of a systolic array with its cells consisting of another systolic array is to be called super-systolic array. This paper proposes a bit-level super-systolic FIR filter with an FPGA-based bit-serial semi-systolic multiplier which twists on the shift and add multiplier by positioning upper and lower half of the serial multiplier side by side physically in floorplanning, instead of linearly. The proposed design is better suited to FPGA implementation than bit-level super-systolic FIR filter with a bit-serial systolic multiplier in each cell in terms of hardware complexity, P&R and performance.
Sponsorship	IEEE Solid-State Circuit Soc. IEEE SSCS Region 10 Chapters
Starting Page	206
Ending Page	209
File Size	263787
Page Count	4
File Format	PDF
ISBN	078038637X
DOI	10.1109/APASIC.2004.1349450
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-08-05
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Concurrent computing High performance computing Circuits Digital signal processing Finite impulse response filter Systolic arrays Hardware Digital filters Field programmable gate arrays Arithmetic
Content Type	Text
Resource Type	Article

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