NDLI: A new RTL debugging methodology in FPGA-based verification platform

Content Provider	IEEE Xplore Digital Library
Author	Sangjun Yang Heejun Shim Wooseung Yang Chong-Min Kyung
Copyright Year	2004
Description	Author affiliation: Dept. of Electr. Eng. & Comput. Sci., KAIST, Daejon, South Korea (Sangjun Yang; Heejun Shim; Wooseung Yang; Chong-Min Kyung)
Abstract	In this paper we present a new RTL debugging methodology in FPGA-based verification platform. This method provides internal node probing in the co-simulation environment. Full observability is guaranteed using 32-bit scan module generated automatically. Most commercial debugging tools are limited to hundreds of internal nodes for the observability in the co-simulation. The proposed method increases the observability of design to 100%. Debugging feature named in RTL gives the benefits that designers feel more comfortable in RTL than in gate level since the signal names in gate level are complicated and incomprehensive. Designers can control the depth of probing in the design hierarchy. The overheads of area and time due to improving the design observability are turned to be small for a reasonable number of internal node probing.
Sponsorship	IEEE Solid-State Circuit Soc. IEEE SSCS Region 10 Chapters
Starting Page	180
Ending Page	183
File Size	441517
Page Count	4
File Format	PDF
ISBN	078038637X
DOI	10.1109/APASIC.2004.1349442
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-08-05
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuits Communication system control Hardware Acceleration Observability Software debugging Software tools Field programmable gate arrays Signal design Flip-flops
Content Type	Text
Resource Type	Article

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