NDLI: HGA: A Hardware-Based Genetic Algorithm

Content Provider	IEEE Xplore Digital Library
Author	Scott, S.D. Samal, A. Seth, S.
Copyright Year	1995
Description	Author affiliation: Washington University, St. Louis, MO (Scott, S.D.)
Abstract	A genetic algorithm (GA) is a robust problem-solving method based on natural selection. Hardware's speed advantage and its ability to parallelize offer great rewards to genetic algorithms. Speedups of 1-3 orders of magnitude have been observed when frequently used software routines were implemented in hardware by way of reprogrammable field-programmable gate arrays (FPGAs). Reprogrammability is essential in a general-purpose GA engine because certain GA modules require changeability (e.g. the function to be optimized by the GA). Thus a hardware-based GA is both feasible and desirable. A fully functional hardware-based genetic algorithm (the HGA) is presented here as a proof-of-concept system. It was designed using VHDL to allow for easy scalability. It is designed to act as a coprocessor with the CPU of a PC. The user programs the FPGAs which implement the function to be optimized. Other GA parameters may also be specified by the user. Simulation results and performance analyses of the HGA are presented. A prototype HGA is described and compared to a similar GA implemented in software. In the simple tests, the prototype took about 6% as many clock cycles to run as the software-based GA. Further suggested improvements could realistically make the HGA 2-3 orders of magnitude faster than the software-based GA.
Starting Page	53
Ending Page	59
File Size	702258
Page Count	7
File Format	PDF
ISBN	0769525504
DOI	10.1109/FPGA.1995.241945
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-02-12
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Software prototyping Scalability Parallel Genetic Algorithms Field Programmable Gate Arrays (FPGAs) Performance Acceleration Engines Genetic algorithms Design optimization Performance Evaluation Hardware Robustness Problem-solving Field programmable gate arrays Function Optimization Coprocessors
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

HGA: a hardware-based genetic algorithm

Parallel Processing on FPGAs: The Effect of Profiling on Performance

Transmuting coprocessors: Dynamic loading of FPGA coprocessors

Performance estimators for hardware/software co-design

Extended genetic algorithm for codesign optimization of DSP systems in FPGAs

Solving the minimum dominating set problem with instance-specific hardware on FPGAs

Development of a flexible hardware core for genetic algorithm

Rapid prototyping and performance evaluation of recoded multipliers using FPGAs

Hardware Acceleration for 3-D Radiation Dose Calculation

HGA: A Hardware-Based Genetic Algorithm

Similar Documents

HGA: a hardware-based genetic algorithm

Parallel Processing on FPGAs: The Effect of Profiling on Performance

Transmuting coprocessors: Dynamic loading of FPGA coprocessors

Performance estimators for hardware/software co-design

Extended genetic algorithm for codesign optimization of DSP systems in FPGAs

Solving the minimum dominating set problem with instance-specific hardware on FPGAs

Development of a flexible hardware core for genetic algorithm

Rapid prototyping and performance evaluation of recoded multipliers using FPGAs

Hardware Acceleration for 3-D Radiation Dose Calculation

HGA: A Hardware-Based Genetic Algorithm