NDLI: Logic Partition Orderings for Multi-FPGA Systems

Content Provider	IEEE Xplore Digital Library
Author	Hauck, S. Borriello, G.
Copyright Year	1995
Description	Author affiliation: University of Washington, Seattle, WA (Hauck, S.)
Abstract	One of the critical issues for multi-FPGA systems is developing software tools for automatically mapping circuits. In this paper we consider one step in this process, partitioning. We describe the task of finding partition orderings, i.e., determining the way in which a circuit should be bipartitioned so as to best map it to a multi-FPGA system. This allows multi-FPGA partitioners to harness standard partitioning techniques. We develop an algorithm for finding partition orderings, which includes a method for increasing parallelism in the process, as well as for including multi-sectioning and multi-way partitioning algorithms. This method is very efficient, and capable of handling most of the current multi-FPGA topologies.
Starting Page	32
Ending Page	38
File Size	124027
Page Count	7
File Format	PDF
ISBN	0769525504
DOI	10.1109/FPGA.1995.241942
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-02-12
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Application specific integrated circuits Computer science Circuit topology Logic circuits Circuit simulation Parallel processing Routing Partitioning algorithms Software tools Field programmable gate arrays
Content Type	Text
Resource Type	Article

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Logic Partition Orderings for Multi-FPGA Systems