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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Thakur, S. Wong, D.F. |
| Copyright Year | 1995 |
| Description | Author affiliation: University ofTexas at Austin (Thakur, S.) |
| Abstract | In this paper, we give a method to design FPGA logic modules, based on an extension of classical work on designing Universal Logic Modules (ULM). Specifically, we give a technique to design a class of logic modules that specialize to a large number of functions under complementations and permutations of inputs, bridging of inputs and assignment of 0/1 to inputs. Thus, a lot of functions can be implemented using a single logic module. The significance of our work lies in our ability to generate a large set of such logic modules. A choice can be made from this set based on design criteria. We demonstrate the technique by generating a set of 471 8-input functions that have a much higher coverage than the 8-input cells employed by Actel's FPGAs. Our functions can specialize to up to 23 times the number of functions that Actel functions can. We also show that by carefully optimizing these functions one can obtain multi-level implementations of them that have delays within 10% of the delays of Actel modules. We demonstrate the effectiveness of these modules in mapping benchmark circuits. We observed a 16% reduction in area and a 21% reduction in delay using our logic modules instead of Actel's on these circuits. |
| Starting Page | 3 |
| Ending Page | 9 |
| File Size | 5214798 |
| Page Count | 7 |
| File Format | |
| ISBN | 0769525504 |
| DOI | 10.1109/FPGA.1995.241856 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1995-02-12 |
| Access Restriction | Subscribed |
| Rights Holder | Association for Computing Machinery, Inc. (ACM) |
| Subject Keyword | Logic design Field programmable gate arrays Logic arrays |
| Content Type | Text |
| Resource Type | Article |
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