NDLI: Design and Implementation of a Delay-Based PUF for FPGA IP Protection

Content Provider	IEEE Xplore Digital Library
Author	Jiliang Zhang Qiang Wu Yongqiang Lyu Qiang Zhou Yici Cai Yaping Lin Gang Qu
Copyright Year	2013
Description	Author affiliation: RIIT&TNList&DCST, Tsinghua Univ., Beijing, China (Yongqiang Lyu; Qiang Zhou; Yici Cai) \|\| Dept. of Electr. & Comput. Eng., Univ. of Maryland, College Park, MD, USA (Gang Qu) \|\| Coll. of Inf. Sci. & Eng., Hunan Univ., Changsha, China (Jiliang Zhang; Qiang Wu; Yaping Lin)
Abstract	Physical Unclonable Function (PUF) makes use of the uncontrollable process variations during the production of IC to generate a unique signature for each IC. It has a wide application in security such as FPGA Intellectual Property (IP) protection, key generation and digital rights management. Ring Oscillator (RO) based PUF and Arbiter-based PUF are the most popular PUFs, but they are not specially designed for FPGA. RO-based PUF incurs high resource overhead while obtaining less challenge-response pairs, and requires ``hard macros'' to implement on FPGA. The arbiter-based PUF brings low resource overhead, but its structure is hard to be mapped on FPGA. Anderson'PUF can address these weaknesses of current Arbiter-based and RO-based PUFs. However, it cannot be directly implemented on the new generation FPGAs, and therefore it has the scalability issue. In order to address these problems, this paper presents a delay-based PUF using the intrinsic structure of FPGA (look-up table and multiplexer). The proposed delay-based PUF is completely realized on 28nm FPGAs. The experimental results show its high uniqueness and reliability. Moreover, we test the proposed PUF in the high temperature, and the results show its availability. Finally, the prospect of the proposed PUF in the FPGA IP protection is discussed.
Starting Page	107
Ending Page	114
File Size	551827
Page Count	8
File Format	PDF
ISBN	9781479925766
DOI	10.1109/CADGraphics.2013.22
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-11-16
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Multiplexing EDA fabrication variation Random access memory Shift registers Table lookup Fabrication FPGAs watermarking hardware security IP cores intellectual property (IP) protection fingerprint Delays Field programmable gate arrays physical unclonable functions (PUFs)
Content Type	Text
Resource Type	Article

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