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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Weinan Zhao Weimin Wu |
| Copyright Year | 2009 |
| Description | Author affiliation: School of Computer and Information Technology, Beijing Jiaotong University, China (Weinan Zhao; Weimin Wu) |
| Abstract | An all-solution Boolean satisfiability (SAT) solver aims to find all the satisfying assignments. In this paper, we introduce ASIG, an all-solution solver for satisfiability problems. ASIG operates on conjunctive normal forms (CNFs) instead of circuits or hybrid representations as most other all-solution solvers did. ASIG prevents the same solution from being found again by creating a blocking clause from a solution and adding it into the clause database. To ensure efficiency, ASIG embeds an incremental mechanism into zchaff [1] to avoid starting search from scratch in searching for a new solution. ASIG also implements some other blocking clause management strategies such as earlier termination and blocking clause merging to further improve efficiency. All our work is tested and analyzed on a set of CNF benchmarks. |
| Starting Page | 508 |
| Ending Page | 513 |
| File Size | 96656 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424436996 |
| DOI | 10.1109/CADCG.2009.5246850 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-08-19 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Electronic design automation and methodology Minimization methods Databases Circuits Merging Benchmark testing Logic design Test pattern generators Information technology Logic testing |
| Content Type | Text |
| Resource Type | Article |
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