NDLI: Novel Differential Flip-Flops Using Neuron-MOS Transistors

Content Provider	IEEE Xplore Digital Library
Author	Guoqiang Hang Xiaohui Hu Danyan Zhang Yang Yang Xiaohu You
Copyright Year	2013
Description	Author affiliation: Sch. of Inf. & Electr. Eng., Zhejiang Univ. City Coll., Hangzhou, China (Guoqiang Hang; Xiaohui Hu; Danyan Zhang; Yang Yang) \|\| Nat. Mobile Commun. Res. Lab., Southeast Univ., Nanjing, China (Xiaohu You)
Abstract	Two new differential flip-flops using neuron-MOS transistors are presented, including one-latch single edge-triggered(IL-SET) flip-flop and one-latch double edge-triggered(IL-DET) flip-flop. In the new differential flip-flops, a pair of n-channel neuron-MOS transistors is used to replace the nMOS logic tree in the conventional differential flip-flops. The construction of the circuits has been simplified by employing the neuron-MOS transistors. In the proposed configurations, the edge-triggering operations are achieved by a narrow pulse produced by two input gates of multiple-input neuron-MOS transistors receiving a clock and a delayed clock, respectively. In comparison with neuron-MOS-based differential master-slave flip-flop, the IL-SET configuration has reduced transistor count and lower power consumption. The HSPICE simulation using TSMC 0.35μm 2-ploy 4-metal CMOS technology validated the effectiveness of the proposed approach.
Starting Page	264
Ending Page	268
File Size	354592
Page Count	5
File Format	PDF
e-ISBN	9781479933815
DOI	10.1109/DASC.2013.73
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-12-21
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS circuit design MOSFET differential circuit neuron-MOS transistor Logic gates Turning Threshold voltage floating-gate MOS flip-flops Flip-flops Clocks
Content Type	Text
Resource Type	Article

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