NDLI: A Radiation Hardened SRAM in 180-nm RHBD Technology

Content Provider	IEEE Xplore Digital Library
Author	Chen Nan Wei Tingcun Wei Xiaomin Chen Xiao
Copyright Year	2013
Description	Author affiliation: Sch. of Comput. Sci. & Technol., Northwestern Polytech. Univ., Xi'an, China (Chen Nan; Wei Tingcun; Wei Xiaomin; Chen Xiao)
Abstract	A 24 kB radiation hardened static random access memory using 180-nm commercial CMOS process appropriate for embedded system on a chip integrated circuits is presented. Radiation-hardened design is realized in the system, circuit and layout design to improve tolerance of radiation effects. The proto chips of SRAM are fabricated and tested, not only the electrical properties of SRAM chips are measured, but also the total ionizing dose effects experiments are finished using a Co-60 gamma radiation source. The experimental results show that, the TID(total ionizing dose effect) tolerance of SRAM chips is larger than 300 krad (Si) in which the electrical functions of SRAM are correct, but with the increase of TID rate, the static and dynamic current of SRAM increase seriously, and the write and read time increase slowly. Furthermore, it is verified by our research that, CMOS transistor layout design with ring-gate and P-type guard ring can enhance the TID tolerance of SRAM greatly.
Starting Page	159
Ending Page	162
File Size	497815
Page Count	4
File Format	PDF
e-ISBN	9781479933815
DOI	10.1109/DASC.2013.55
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-12-21
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Guard Ring SRAM chips Layout Logic gates Radiation Hardened by Design Ring-gate Electron tubes Arrays SRAM MOS devices Total Ionizing Dose Effect
Content Type	Text
Resource Type	Article

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