NDLI: An FPGA-based interface for recording high-speed data stream

Content Provider	IEEE Xplore Digital Library
Author	Sun Zhaoyan Dong Yonggui Guo Wenxiu Xiong Xanping Ma Cheng Jia Huibo Feng Guanping
Copyright Year	2002
Description	Author affiliation: Dept. of Precision Instrum., Tsinghua Univ., Beijing, China (Sun Zhaoyan; Dong Yonggui; Guo Wenxiu; Xiong Xanping; Ma Cheng; Jia Huibo; Feng Guanping)
Abstract	An FPGA-based interface for recording high-speed continuous data stream is introduced. The original data stream is input to the interface and reconstructed to four low-speed data streams. Synchronously, by calculating the XOR value of the four corresponding data streams, one checkout code stream is generated. On the other hand, the interface can inversely recover the original data stream while reading. Moreover, when one of the recorded data streams is unreadable, the interface can restore the data stream with the assist of the checkout codes. As the core of this interface, one FPGA chip is selected to implement all the corresponding algorithms. Experimental results show that the interface can work perfectly under the clock of 80 MHz.
Sponsorship	Chinese Inst. Commun Chinese Inst. Electron. Univ. Electron. Sci. & Technol. China
Starting Page	1466
Ending Page	1470
File Size	274623
Page Count	5
File Format	PDF
ISBN	0780375475
DOI	10.1109/ICCCAS.2002.1179056
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-06-29
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Instruments Optical recording Reconstruction algorithms Synchronous generators Sun Field programmable gate arrays Clocks Pipeline processing Disk recording Magnetic recording
Content Type	Text
Resource Type	Article

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