NDLI: Introducing redundant transformations for built-in self-testable data path allocation

Content Provider	IEEE Xplore Digital Library
Author	Yang, L.T. Muzio, J.
Copyright Year	2002
Description	Author affiliation: Dept. of Comput. Sci., Saint Francis Xavier Univ., Antigonish, NS, Canada (Yang, L.T.)
Abstract	In our previous work, we described a high-level data path allocation algorithm to facilitate built-in self-test designs. In this paper, we make use of two types of redundant transformations, which add redundancy that improves test resources to be shared in the data path, to improve our previous data path allocation algorithm. The algorithm generates self-testable data path design while maximizing the sharing of modules and test registers. The sharing of modules and test registers enables only a small number of registers to be modified for BIST, thereby decreasing the hardware area which is one of the major overheads for the BIST technique. With a variety of benchmarks, we demonstrate the advantage of our approach compared with our previous and other conventional approaches.
Sponsorship	Chinese Inst. Commun Chinese Inst. Electron. Univ. Electron. Sci. & Technol. China
Starting Page	1346
Ending Page	1350
File Size	419329
Page Count	5
File Format	PDF
ISBN	0780375475
DOI	10.1109/ICCCAS.2002.1179031
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-06-29
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis Built-in self-test Hardware Iterative algorithms Registers Test pattern generators Resource management Circuit testing Logic testing Digital circuits
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Built-in self-testable data path synthesis

Signature analysis and test scheduling for self-testable circuits

High-level data path synthesis for built-in self-test designs

A high-level data path allocation algorithm based on BIST testability metrics

Introducing redundant transformations for high level built-in self-testable synthesis

Error masking in self-testable circuits

The design of random-testable sequential circuits

Data path synthesis for BIST with low area overhead

Built-In Test for Complex Digital Integrated Circuits

Introducing redundant transformations for built-in self-testable data path allocation

Similar Documents

Built-in self-testable data path synthesis

Signature analysis and test scheduling for self-testable circuits

High-level data path synthesis for built-in self-test designs

A high-level data path allocation algorithm based on BIST testability metrics

Introducing redundant transformations for high level built-in self-testable synthesis

Error masking in self-testable circuits

The design of random-testable sequential circuits

Data path synthesis for BIST with low area overhead

Built-In Test for Complex Digital Integrated Circuits

Introducing redundant transformations for built-in self-testable data path allocation