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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Qiang Wu Yunfeng Wang Jinian Bian Weimin Wu Hongxi Xue |
| Copyright Year | 2002 |
| Description | Author affiliation: Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China (Qiang Wu; Yunfeng Wang; Jinian Bian; Weimin Wu; Hongxi Xue) |
| Abstract | A hierarchical CDFG model designed as an intermediate representation for hardware/software (HW/SW) codesign is presented in this paper. A new concept of transport node, which represents the communication resources of the system, is proposed in this model. Hierarchical feature can be straightly obtained through extending the definition of nodes, allowing them to nest sub-CDFG recursively. Then it is demonstrated how to build basic control constructs of branches and loops. Explaining in a short introduction to the translation process, such a hierarchical CDFG is suitable for HW/SW codesign as an intermediate representation. The hierarchical CDFG model can capture the design information from source file specified by VHDL or C language. It maintains relative simplicity while providing helpful features for HW/SW partitioning and High-level synthesis tools. |
| Sponsorship | Chinese Inst. Commun Chinese Inst. Electron. Univ. Electron. Sci. & Technol. China |
| Starting Page | 1429 |
| Ending Page | 1432 |
| File Size | 264512 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780375475 |
| DOI | 10.1109/ICCCAS.2002.1179048 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2002-06-29 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Computer science Synthesizers Wires Communication system control Control system synthesis Hardware High level synthesis Specification languages Flow graphs Research and development |
| Content Type | Text |
| Resource Type | Article |
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