NDLI: The ARISE Reconfigurable Instruction Set Extensions Framework

Content Provider	IEEE Xplore Digital Library
Author	Vassiliadis, N. Theodoridis, G. Nikolaidis, S.
Copyright Year	2007
Description	Author affiliation: Aristotle Univ. of Thessaloniki, Thessaloniki (Vassiliadis, N.; Theodoridis, G.; Nikolaidis, S.)
Abstract	In this paper, we introduce the ARISE framework for the systematic extension of typical processors with the necessary infrastructure to support arbitrary number and type of reconfigurable hardware units. ARISE extends the micro-architecture of the processor with an interface to allow the coupling of the hardware units. Furthermore, the instruction set of the processor is extended with instructions which expose to the programmer/compiler the full control of the interface. This control includes the configuration of operations on the hardware units, execution of these operations, and communication of data between the processor and the units. The new instructions are incorporated without the need to redesign the processor instruction set architecture. To evaluate our proposal a model of an ARISE extended MIPS processor has been designed. Using a turbodecoder algorithm as benchmarking application a simulation of the ARISE model has been performed. Performance results show impressive application speedups up to times7.5.
Starting Page	153
Ending Page	160
File Size	3480383
Page Count	8
File Format	PDF
ISBN	1424410584
DOI	10.1109/ICSAMOS.2007.4285746
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-07-16
Publisher Place	Greece
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Process design Computer aided instruction Program processors Microarchitecture Physics computing Communication system control Hardware Explosions Proposals Programming profession
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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