NDLI: Performance and Power Analysis of Parallelized Implementations on an MPCore Multiprocessor Platform

Content Provider	IEEE Xplore Digital Library
Author	Blume, H. Livonius, J.v. Rotenberg, L. Noll, T.G. Bothe, H. Brakensiek, J.
Copyright Year	2007
Description	Author affiliation: RWTH Aachen Univ., Aachen (Blume, H.; Livonius, J.v.; Rotenberg, L.; Noll, T.G.)
Abstract	In this contribution, the potential of parallelized software that implements algorithms of digital signal processing on a multicore processor platform is analyzed. For this purpose various digital signal processing tasks have been implemented on a prototyping platform i.e. an ARM MPCore featuring four ARM 11 processor cores. In order to analyze the effect of parallelization on the resulting performance-power ratio, influencing parameters like e.g. the number of issued program threads have been studied. For paralllelization issues the OpenMP programming model has been used which can be efficiently applied on C- level. In order to elaborate power efficient code also a functional and instruction level power model of the MPCore has been derived which features a high estimation accuracy. Using this power model and exploiting the capabilities of OpenMP a variety of exemplary tasks could be efficiently parallelized. The general efficiency potential of parallelization for multiprocessor architectures can be assembled.
Starting Page	74
Ending Page	81
File Size	13594613
Page Count	8
File Format	PDF
ISBN	1424410584
DOI	10.1109/ICSAMOS.2007.4285736
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-07-16
Publisher Place	Greece
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis Software prototyping Multicore processing Multicore Processors Software algorithms Power Estimation and Optimization Yarn Signal processing algorithms Prototypes Digital signal processing Performance analysis Signal analysis Parallelization
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Taurus: a multiprocessor DSP prototyping environment

Rapid prototyping on the Georgia Tech digital signal multiprocessor

Power estimation methodology for VLIW Digital Signal Processors

Novel parallel Hough Transform on multi-core processors

Evaluation of parallelization of an image processing algorithm for an embedded multicore platform using manual parallelization and the OpenMP parallel framework

A rapid turn-around system for designing efficient fine grained signal processors

A framework for low power audio design

The Rapid Prototyping of Application Specific Signal Processors (RASSP) program: overview and status

DSP performance evaluation for motion estimation

Performance and Power Analysis of Parallelized Implementations on an MPCore Multiprocessor Platform

Similar Documents

Taurus: a multiprocessor DSP prototyping environment

Rapid prototyping on the Georgia Tech digital signal multiprocessor

Power estimation methodology for VLIW Digital Signal Processors

Novel parallel Hough Transform on multi-core processors

Evaluation of parallelization of an image processing algorithm for an embedded multicore platform using manual parallelization and the OpenMP parallel framework

A rapid turn-around system for designing efficient fine grained signal processors

A framework for low power audio design

The Rapid Prototyping of Application Specific Signal Processors (RASSP) program: overview and status

DSP performance evaluation for motion estimation

Performance and Power Analysis of Parallelized Implementations on an MPCore Multiprocessor Platform