NDLI: Verilog-a compact semiconductor device modelling and circuit macromodelling with the QucsStudio-ADMS “turn-key” modelling system

Content Provider	IEEE Xplore Digital Library
Author	Brinson, M.E. Margraf, M.
Copyright Year	2012
Description	Author affiliation: Qucs and QucsStudio Project Founder, Berlin, Germany (Margraf, M.) \|\| Centre for Communications Technology, London Metropolitan University, N78DB, UK (Brinson, M.E.)
Abstract	The Verilog-A “Analogue Device Model Synthesizer” (ADMS) has in recent years become an established modelling tool for GNU General Public License circuit simulator development. Qucs and ngspice being two examples of open source circuit simulators that use ADMS. This paper presents a “turn-key” compact device modelling and circuit macromodelling system based on ADMS and implemented in the QucsStudio circuit design, simulation and manufacturing environment. A core feature of the new system is a modelling procedure which does not require users to manually patch the circuit simulator C++ code. At the start of a QucsStudio simulation the software automatically detects any changes in Verilog-A model code, re-compiling and dynamically linking the modified code to the body of the QucsStudio code. The inherent flexibility of the “turn-key” system encourages rapid experimentation with analogue and RF compact device models. In this paper QucsStudio “turn-key” modelling is illustrated by the design of a single stage RF amplifier circuit.
Starting Page	94
Ending Page	99
File Size	265909
Page Count	6
File Format	PDF
ISBN	9781457720925
e-ISBN	9788393207589
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-05-24
Publisher Place	Poland
Access Restriction	Subscribed
Rights Holder	Dept of Microelectronics
Subject Keyword	Radio frequency Semiconductor device modeling turn-key component modelling compact device modelling ADMS Software Libraries QucsStudio Mathematical model Integrated circuit modeling Hardware design languages Verilog-A
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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