NDLI: Real-time implementation of noise-immune gradient-based edge detection

Content Provider	IEEE Xplore Digital Library
Author	Pei-Yung Hsiao Hwa Wen Ying-Pei Chen Sao-Jie Chen
Copyright Year	2005
Description	Author affiliation: Dept. of Electron. Eng., Chang Gung Univ., Tao Yuan, Taiwan (Pei-Yung Hsiao; Hwa Wen)
Abstract	This paper describes the implementation of a computational FPGA for edge detection, which particularly is immune to noise by a digital approximated Gaussian smoothing filter. Proposed systolic array architecture has been examined for convolution operation, which benefits the design with simplicity and regularity. Moreover, most of the presented processing structures are highly pipelined thus the goal of a real-time computing is substantially achieved with a frame rate up to 202 frames/sec. For the efficiency of hardware mapping to certain algorithm, the absolute difference mask (ADM) is adopted for its regularity and independent operations, as well as the valuable property of performing one-pixel-edge localization. A scalable FIFO design is also proposed, which makes the edge detector applicable for five different image sizes. The FPGA implementation on a versatile development platform results that our design improves the speed and hardware usage. This is attributed to the utilization of the proposed parallel and pipelined structure, so that a fast operation speed of 53MHz is obtained in this investigation, which is 83 times faster than software implementation.
Starting Page	633
Ending Page	636
File Size	800957
Page Count	4
File Format	PDF
ISBN	0780390296
DOI	10.1109/ISSCS.2005.1511320
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-07-14
Publisher Place	Romania
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Smoothing methods Convolution Image edge detection Gaussian noise Computer architecture Detectors Hardware Systolic arrays Digital filters Field programmable gate arrays
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

An improved real-time hardware architecture for Canny edge detection based on FPGA

FPGA based architecture for realtime edge detection

An IP Approach to Real Time Edge Detection

FPGA Implementation of Real-Time Edge-Preserving Filter for Video Noise Reduction

A real time video smoothing implementation inside an FPGA-based system

Separable convolution gaussian smoothing filters on a xilinx FPGA platform

An Image Processing Architecture to Exploit I/O Bandwidth on Reconfigurable Computers

Lane Detection Using Steerable Filters and FPGA-based Implementation

FPGA-based customizable systolic architecture for image processing applications

Real-time implementation of noise-immune gradient-based edge detection

Similar Documents

An improved real-time hardware architecture for Canny edge detection based on FPGA

FPGA based architecture for realtime edge detection

An IP Approach to Real Time Edge Detection

FPGA Implementation of Real-Time Edge-Preserving Filter for Video Noise Reduction

A real time video smoothing implementation inside an FPGA-based system

Separable convolution gaussian smoothing filters on a xilinx FPGA platform

An Image Processing Architecture to Exploit I/O Bandwidth on Reconfigurable Computers

Lane Detection Using Steerable Filters and FPGA-based Implementation

FPGA-based customizable systolic architecture for image processing applications

Real-time implementation of noise-immune gradient-based edge detection