NDLI: Self-calibrating floating-point analog-to-digital converter

Content Provider	IEEE Xplore Digital Library
Author	Groza, V. Debski, M.
Copyright Year	2005
Description	Author affiliation: Sch. of Inf. Technol. & Eng., Ottawa Univ., Ont., Canada (Groza, V.; Debski, M.)
Abstract	The floating-point analog-to-digital converter (FPADC) is an extended version of the fixed-point ADC. It is designed to deal with a broader dynamic range of signals while exhibiting a smaller relative quantization error. The traditional implementation of the FPADC requires high-precision high-speed components in order to achieve these characteristics for high sampling rates. The paper introduces a new high-speed high-precision FPADC that employs low-grade components whose errors are compensated through a low-speed high-precision calibration mechanism. The precision is maintained at high values by additional hardware that periodically performs calibration cycles. A hybrid hardware-software implementation of the design is carried out and described. Finally, experimental measurements are performed to compare the characteristics of the new FPADC.
Starting Page	287
Ending Page	290
File Size	742032
Page Count	4
File Format	PDF
ISBN	0780390296
DOI	10.1109/ISSCS.2005.1509910
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-07-14
Publisher Place	Romania
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Automatic testing Quantization Dynamic range Built-in self-test Sampling methods Calibration Error correction Information technology Analog-digital conversion Signal design
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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