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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Yuan, J. Piper, J. |
| Copyright Year | 1999 |
| Description | Author affiliation: Dept. of Appl. Electron., Lund Univ., Sweden (Yuan, J.) |
| Abstract | A floating-point ADC (FP-ADC) has been proposed for the purpose of achieving a wide dynamic range without demanding a high resolution, when the high resolution is merely for covering the signal dynamic range rather than the quantization accuracy. In an FP-ADC, the dynamic range and resolution can be designed independently. Unlike the known logarithmic amplifier solution, it directly gives a linear digital output. It can work with a small input range imposed by a low voltage supply as its virtual input range is greatly expanded. The principle, key circuitry, achievable performance and sensitivities to mismatches are addressed in this paper. Simulation results indicate that this approach is capable of achieving up to a 16 bit dynamic range with an 8-10 bit effective resolution at a sampling rate of 40 MS/s in submicron CMOS. |
| Starting Page | 1385 |
| Ending Page | 1388 |
| File Size | 399546 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780356829 |
| DOI | 10.1109/ICECS.1999.814428 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1999-09-05 |
| Publisher Place | Cyprus |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Analog-digital conversion Signal resolution Dynamic range Quantization Low voltage Sampling methods Signal design CMOS technology Circuit synthesis Circuit simulation |
| Content Type | Text |
| Resource Type | Article |
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