NDLI: A parity checker for a large residue numbers based on Montgomery reduction method

Please wait, while we are loading the content...

2015 International Symposium on Signals, Circuits and Systems (ISSCS)

International Symposium on Signals, Circuits and Systems ISSCS2013

ISSCS 2011 - International Symposium on Signals, Circuits and Systems

2009 International Symposium on Signals, Circuits and Systems

2007 International Symposium on Signals, Circuits and Systems

International Symposium on Signals, Circuits and Systems, 2005. ISSCS 2005.

Volume 2 - 2005

Volume 1 - 2005

ISSCS 2005. International Symposium on Signals, Circuits and Systems (IEEE Cat. No. 05EX1038)

IEEE ISSCS 2005 - International Symposium on Signals, Circuits and Systems - Volume 1

Co-sponsorship's provided by:

Chair's and Committees

Table of contents - Volume 1

Scaling theory and "punctuated equilibrium" in CMOS technology

Challenges and opportunities of silicon technology in communications

This page was intentionally left blank

Technological and architectural power optimizations for advance microprocessors

Real-time threshold-voltage control scheme for low-power VLSI under fluctuation of a supply voltage

Energy-efficient encoding for HDCP protected digital LCD interfaces

Power-efficient superior-order curvature corrected voltage reference using CMOS computational circuits

Limits for switching power consumption in encoded interconnects

Segmentation of thoracic computed tomography images

Mean field annealing for motion estimation in medical image sequences

Automatic segmentation of the heart muscle from echocardiographic images

On the influence of image enhancement on fractal-based automatic osteoporosis detection from calcaneum x-rays

Comparison of histogram-based feature sets for medical image modality categorization

Trading off power versus latency using GPLS clocking in 2D-mesh NoCs

Asynchronous network node design for network-on-chip

Evaluating the relative effect of process variations and switching patterns on bus performance towards nano-scale interconnects

Distributed arbitration for the segmented-bus platform

Starvation-free arbitration policies for the segmented-bus platform

Buffer constraints for rate-distortion optimization in mobile video communications

Randomness analysis of images of aggregates

Skin detection and tracking by monocular vision

On the regularization of segmented satellite images

A comparison of multispectral satellite sequence compression approaches

On a hardware architecture for the evolution of cellular automata functionality

Parallel 4/spl times/4 transform architecture based on bit extended arithmetic for H.264/AVC

Row-column decomposition based 2D transform optimization on subword parallel processors

Automated design of FFT/IFFT processors for advanced telecom applications

A novel pipelined multiplier for high-speed DSP applications

An efficient null steering broadband beamformer

Towards the development of a hardware simulator for MIMO radio channels

GSM channel estimator using a fixed-point matrix inversion algorithm

Nonlinearity analysis of power detectors in direct conversion receivers utilizing six-port technology

Handover initiation and decision criteria for the fourth generation radio-mobile networks

Design and simulation of RF MEMS cantilever and bridge switches for high switching speed and low voltage operation and their comparison

On the study of a digitally calibrated R-2R ladder architecture

Signal conditioning for capacitive sensors with field programmable analog arrays

A simple circuit for sigma-delta/delta modulation

Theorems of parameter variations applied for the extraction of compact models of on-chip passive structures

The design of a low-distortion sigma-delta ADC for WLAN standards

Sampling set conditions for shift-invariant signal spaces

This page was intentionally left blank

Reconstruction in lattice-invariant signal spaces

This page was intentionally left blank

Spectral matching accuracy in processing hyperspectral data

An efficient systolic array algorithm for the VLSI implementation of a prime-length DHT

This page was intentionally left blank

Testing the statistical independence of continuous random variables: a new robust algorithm

Efficient LSP computation and quantization

Matrix framework for analysis of invariant sets

n-dimensional k-order systems: computing the transfer function

Circuit diakoptic analysis based on order reduction of state equations

Numerical simulation of discrete time circuits taking into account weakly nonlinear effects

Automatization of compression point 1dB (CP1dB) and input 3rd order intercept point (IIP3) measurements using lab VIEW platform

Fault detection and diagnosis for reaction wheels of satellite's attitude control system using a bank of Kalman filters

Spatio temporal characteristics of the human color perception for digital quality assessment

Integration of human perception for color texture management

Gray level image enhancement using piecewise linear functions

Color image enhancement method using three parameters affine transform

Driver monitoring with a single high-speed camera and IR illumination

Color-based semantic characterization of cartoons

Generating identically and independently distributed samples starting from chaotic signals

Information analysis of the NRZ-M line codes and their generalization

A new design technique for optimum logic filter using matrix type-B error correcting coding

Performance analysis of DFE magnetic recording channels with RLL encoding constraints

A new image encryption algorithm based on inversable functions defined on Galois fields

High-rate DC-free ternary runlength-limited codes

Volterra kernel interpolation for system modeling and predistortion purposes

UWB transceiver circuits design for WPANs applications

Single-chip heterodyne receiver for 5-6 GHz WLAN with high image rejection

A simulation comparison of distributed power control algorithms for wireless communications

Wireless LAN medium access techniques QoS perspective

Simulation model for WLAN and GSM interoperating

A 3.3-V wideband high-precision fully differential CMOS track and hold amplifier

A 0.6V multi-V/sub t/ current mirror differential OTA

Switching-based topologies for high-efficiency audio amplifiers

Self-calibrating floating-point analog-to-digital converter

Fully differential CMOS current memory cell for analog-to-digital converters

Simplified "sinh" current mode lossy ELIN integrator

Spectral perturbation parameters for voice pathology detection

A reusable HMM soft-core for isolated word recognition

Inter-dependence of spectral measures for the singing voice

Multi-band Bark scale spectral over-subtraction for colored noise reduction

On speech signals reconstruction from local extreme values

Nullor network Jacobian and Hessian matrices: symbolic determination by using Chan-Mai signal-flow graphs

When is the fast computation of the periodic steady state appropriate

Behavioral model generation for symbolic analysis of analog integrated circuits

Novel design method of analog all-pass filters

Design of active filters simulating mesh current equation of LC ladder filters

A new approach to discrete conical curves

Human-computer interaction: a Bayesian network approach

Color image segmentation using steerable filters

Approximation of a linear shift-variant system by a set of linear shift-invariant systems

A parity checker for a large residue numbers based on Montgomery reduction method

Optimizations in max-log-MAP LLR/sup e/ VLSI architecture

The performances of interleavers used in turbo codes

A study on turbo coding systems with /spl pi//4 shifted DQPSK modulation

Decreasing of the turbo MAP decoding time using an iterations stopping criterion

A 90 nm CMOS 10 GHz beam forming transmitter

A novel fully integrated antenna switch for 5-6 GHz wireless LAN systems

A 5-GHz low-voltage and low-power CMOS LC VCO for 802.11a wireless LAN applications

Low-voltage, low-power and highly-tunable 1.8GHz CMOS LC voltage controlled oscillator

Memory management in output-buffering packet-switch design

Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on

A parity checker for a large residue numbers based on Montgomery reduction method

Content Provider	IEEE Xplore Digital Library
Author	Jung-Hee Suk Jin-Seon Youn Hui-Gon Kim Taek-Won Kwon Jun-Rim Choi
Copyright Year	2005
Description	Author affiliation: Sch. of Electr. Eng. & Comput. Sci., Kyungbook Nat. Univ., Daegu, South Korea (Jung-Hee Suk; Jin-Seon Youn; Hui-Gon Kim; Taek-Won Kwon; Jun-Rim Choi)
Abstract	Fast and simple algorithm of a parity checker for a large residue numbers is presented. A new set of RNS moduli with 2/sup r/- (2/sup l//spl plusmn/ 1) form for fast modular multiplication is proposed. The proposed RNS moduli has a large dynamic range for a large RNS number. The parity of a residue number can be checked by the Chinese remainder theorem (CRT). A CRT-based parity checker is simply organized by the Montgomery reduction method (MRM), implemented by using multipliers and the carry-save adder array. We present a fast parity checker with minimal hardware processed in three clock cycles for 32-bit RNS modulus set.
Starting Page	355
Ending Page	358
File Size	695566
Page Count	4
File Format	PDF
ISBN	0780390296
DOI	10.1109/ISSCS.2005.1509927
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-07-14
Publisher Place	Romania
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer science Graphics Cathode ray tubes Dynamic range Hardware Cryptography Read only memory Arithmetic Clocks
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in