NDLI: Implementation and verification of DPA-resistant cryptographic DES circuit using Domino-RSL

Content Provider	IEEE Xplore Digital Library
Author	Iwai, K. Shiozaki, M. Anh-Tuan Hoang Kojima, K. Fujino, T.
Copyright Year	2011
Description	Author affiliation: Department of Science and Engineering, Ritsumeikan University, 1-1-1 Nojihigashi, Kusatsu, Shiga, 525-8527, Japan (Fujino, T.) \|\| Research Organization of Science and Engineering, Ritsumeikan University, 1-1-1 Nojihigashi, Kusatsu, Shiga, 525-8527, Japan (Shiozaki, M.; Anh-Tuan Hoang) \|\| Graduate School of Science and Technology, Ritsumeikan University, 1-1-1 Nojihigashi, Kusatsu, Shiga, 525-8527, Japan (Iwai, K.; Kojima, K.)
Abstract	Differential Power Analysis (DPA) which is one of the Side-Channel Attack techniques can easily extract the secret information such as a cryptographic key from the device by analyzing the power consumption. Some DPA-resistant techniques have been proposed to protect the secret information. However, these techniques require special CADs, which balance wiring capacitance and control the timing to activate the logics for enabling signals. We have proposed a DPA-resistant Domino-RSL technique to design and implement by the standard CAD tool easily. This DPA resistance is achieved by eliminating the correlation between power consumption and cryptography operation. In this paper, the design flow of the Domino-RSL technique is presented and the DPA resistance of a DES circuit, which was designed and fabricated with 0.18μm CMOS technology, is evaluated using the Side-channel Attack Standard Evaluation Board (SASEBO). The Domino-RSL DES circuit did never reveal the secret key even with 100,000 wave samples analysis.
Starting Page	28
Ending Page	33
File Size	1579448
Page Count	6
File Format	PDF
ISBN	9781457710599
e-ISBN	9781457710582
DOI	10.1109/HST.2011.5954991
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-06-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Power demand Side-Channel Attack Domino-RSL RSL Resistance SASEBO DES Layout Logic gates Timing Cryptography Hardware design languages WDDL Differential Power Analysis
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in