NDLI: ODETTE: A non-scan design-for-test methodology for Trojan detection in ICs

Content Provider	IEEE Xplore Digital Library
Author	Banga, M. Hsiao, M.S.
Copyright Year	2011
Description	Author affiliation: Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, Virginia - 24061 (Banga, M.; Hsiao, M.S.)
Abstract	In this paper, we propose a two-step non-scan design-for-test methodology that can ease detection of an embedded Trojan and simultaneously partially obfuscates a design against Trojan implantations. In the first step, we use Q signals of flip-flops in a circuit to increase the number of reachable states. In the second step, we partition these flip-flops into different groups enhancing the state-space variation. Creation of these new reachable states helps to trigger and propagate the Trojan effect more easily. Experimental results on ISCAS'89 benchmarks show that this method can effectively uncover Trojans which are otherwise very difficult to detect in the normal functional mode. In addition, partitioning the flip-flops of the circuit into different groups and selecting the output (Q or Q) based on input controlled ENABLE signals conceal its actual functionality beyond simple recognition thereby making it difficult for the adversary to implant Trojans.
Starting Page	18
Ending Page	23
File Size	304837
Page Count	6
File Format	PDF
ISBN	9781457710599
e-ISBN	9781457710582
DOI	10.1109/HST.2011.5954989
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-06-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Integrated circuits Multiplexing Logic gates Pins Trojan horses Delay
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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