NDLI: Accelerating early design phase differential power analysis using power emulation techniques

Content Provider	IEEE Xplore Digital Library
Author	Krieg, A. Bachmann, C. Grinschgl, J. Steger, C. Weiss, R. Haid, J.
Copyright Year	2011
Description	Author affiliation: Institute for Technical Informatics, Graz University of Technology, Austria (Krieg, A.; Bachmann, C.; Grinschgl, J.; Steger, C.; Weiss, R.) \|\| Design Center Graz, Infineon Technologies Austria AG, Graz, Austria (Haid, J.)
Abstract	The personal banking and ID sector has seen a tremendous change in recent years, partially caused by the widespread introduction of smart-cards. Because of the extensive implications of a successful attack on these devices, a wide range of practical as well as purely academic attacks has been developed during the last years. These attacks have unveiled weaknesses in hardware as well as software implementations of several different, partially widely used cryptographic algorithms. An especially powerful method, the differential power analysis (DPA), extracts secret information from power consumption and electro-magnetic emission profiles. The efficiency of a DPA attack significantly depends on the quality of the cryptographic algorithm implementation. These traces currently can only be generated using real hardware or simulation-based approaches. Depending on the chosen simulation accuracy these evaluations result in time-consuming RTL and SPICE simulations often limiting the maximum amount of available execution traces. This paper introduces a novel high-speed methodology for early security evaluations of integrated processor systems using power emulation. First, the usage of power emulation hardware allows for the estimation of attack effort that an adversary will have to invest to gain secret information from an algorithm's execution profile. Second, countermeasures against differential power analysis attacks can be quickly evaluated in terms of effectiveness. The shown approach uses semi-automatic characterization techniques and fully synthesizable emulation hardware to reduce the designer's dependency on time-consuming simulation runs.
Starting Page	81
Ending Page	86
File Size	309275
Page Count	6
File Format	PDF
ISBN	9781457710599
e-ISBN	9781457710582
DOI	10.1109/HST.2011.5955001
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-06-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Adaptation models Power demand Emulation Hardware Software Cryptography Field programmable gate arrays
Content Type	Text
Resource Type	Article

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