NDLI: B-spline generation in FPGA

Content Provider	IEEE Xplore Digital Library
Author	da Silva, L.M.C. de Paiva, M.S.V.
Copyright Year	2012
Description	Author affiliation: Electrical Engineering Department, Federal University of Technology - Paraná, Cornélio Procópio - Paraná - Brazil (da Silva, L.M.C.) \|\| Electrical Engineering Department, USP - University of São Paulo, São Carlos - São Paulo - Brazil (de Paiva, M.S.V.)
Abstract	B-spline curves can represent almost any smooth shape, being adopted by file exchange standards, used as a wavelet basis for multiresolution systems and manufacturing efficiency is increased using b-splines toolpaths. The respective algorithms for conventional CPUs demand great computational effort, requiring another hardware architectures, like GPUs, for better processing efficiency. This paper describes a system on a chip that generates b-splines curves from given control points in a concurrent way, based in a FPGA platform, including features that are not addressed by the few works in the area. This system is faster than a quadcore CPU in the order of the number of generated points, at the same clock rate. The independence of the number of generated and initial control points, and the processing determined by the FPGA capacity, makes it a better choice for embedded systems in relation to conventional CPUs.
Starting Page	1
Ending Page	5
File Size	554250
Page Count	5
File Format	PDF
ISBN	9781467301848
e-ISBN	9781467301862
DOI	10.1109/SPL.2012.6211798
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-03-20
Publisher Place	Spain
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Surface reconstruction reconfigurable logic curves surface FPGA b-spline Three dimensional displays Spline Field programmable gate arrays Surface treatment Graphics processing unit
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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