NDLI: 3D FFTs on a Single FPGA

Content Provider	IEEE Xplore Digital Library
Author	Humphries, B. Hansen Zhang Jiayi Sheng Landaverde, R. Herbordt, M.C.
Copyright Year	2014
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Boston Univ., Boston, MA, USA (Humphries, B.; Hansen Zhang; Jiayi Sheng; Landaverde, R.; Herbordt, M.C.)
Abstract	The 3D FFT is critical in many physical simulations and image processing applications. On FPGAs, however, the 3D FFT was thought to be inefficient relative to other methods such as convolution-based implementations of multigrid. We find the opposite: a simple design, operating at a conservative frequency, takes 4μs for $16^{3},$ 21μs for $32^{3},$ and 215μs for $64^{3}$ single precision data points. The first two of these compare favorably with the 25μs and 29μs obtained running on a current Nvidia GPU. Some broader significance is that this is a critical piece in implementing a large scale FPGA-based MD engine: even a single FPGA is capable of keeping the FFT off of the critical path for a large fraction of possible MD simulations.
Starting Page	68
Ending Page	71
File Size	267662
Page Count	4
File Format	PDF
e-ISBN	9781479951116
DOI	10.1109/FCCM.2014.28
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-05-11
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Random access memory Three-dimensional displays IP networks Graphics processing units Pipelines Generators FFT High Performance Reconfigurable Computing
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

3D FFT for FPGAs

Limits of FPGA acceleration of 3D Green's Function computation for geophysical applications

Mapping 1D-FFT on an energy efficient 3D FPGA-DRAM architecture

From GPU to FPGA: A Pipelined Hierarchical Approach to Fast and Memory-Efficient NDN Name Lookup

A FPGA architecture for real-time processing of variable-length FFTS

High-throughput IP-lookup supporting dynamic routing tables using FPGA

Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA

Architecture and performance evaluation of 3D CMOS-NEM FPGA

3D-NonFAR: Three-dimensional non-volatile FPGA architecture using phase change memory

3D FFTs on a Single FPGA

Similar Documents

3D FFT for FPGAs

Limits of FPGA acceleration of 3D Green's Function computation for geophysical applications

Mapping 1D-FFT on an energy efficient 3D FPGA-DRAM architecture

From GPU to FPGA: A Pipelined Hierarchical Approach to Fast and Memory-Efficient NDN Name Lookup

A FPGA architecture for real-time processing of variable-length FFTS

High-throughput IP-lookup supporting dynamic routing tables using FPGA

Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA

Architecture and performance evaluation of 3D CMOS-NEM FPGA

3D-NonFAR: Three-dimensional non-volatile FPGA architecture using phase change memory

3D FFTs on a Single FPGA