NDLI: Body-raised double-gate structure for 1T DRAM

Content Provider	IEEE Xplore Digital Library
Author	Garam Kim Sang Wan Kim Jae Young Song Jong Pil Kim Kyung-Chang Ryoo Jeong-Hoon Oh Jae Hyun Park Hyun Woo Kim Byung-Gook Park
Copyright Year	2009
Description	Author affiliation: Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering, Seoul National University, San 56-1, Shinlim-dong, Kwanak-gu, 151-742, Korea (Garam Kim; Sang Wan Kim; Jae Young Song; Jong Pil Kim; Kyung-Chang Ryoo; Jeong-Hoon Oh; Jae Hyun Park; Hyun Woo Kim; Byung-Gook Park)
Abstract	Higher sensing margin and longer retention time are critical issues for commercializing 1T DRAM. In this paper, we propose a body-raised double-gate structure to improve sensing margin and retention time of 1T DRAM and confirm the improvements through 3D simulation. This structure shows about 20% higher sensing margin than the planar structure. We have achieved longer retention time by using high doped raised body and lowering the magnitude of gate bias at hold state.
Starting Page	259
Ending Page	263
File Size	4934558
Page Count	5
File Format	PDF
ISBN	9781424446957
DOI	10.1109/NMDC.2009.5167556
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-06-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Z-RAM Semiconductor materials Capacitors Random access memory Doping SOI Raised body USA Councils Cities and towns Capacitance Impact ionization 1T DRAM Commercialization Nanotechnology
Content Type	Text
Resource Type	Article

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