NDLI: Cost effective RISC core supporting the large sending offload

Content Provider	IEEE Xplore Digital Library
Author	Elbeshti, M. Dixon, M. Koziniec, T.
Copyright Year	2012
Description	Author affiliation: School of IT, Murdoch Uni, Perth, Australia (Elbeshti, M.; Dixon, M.; Koziniec, T.)
Abstract	The Ethernet speed has increased sending and receiving frames from 40 to 100 Gbps after the IEEE P802.3ba released. The industry and academia have focused scaling up the TCP/IP protocol processing for 40–100 Gbps. LSO is a de facto standard, which is offloaded to network interface for sending packets up to 10 Gbps. It not clears whether a network interface can support such function for new 40–100 Gbps. The widely use of the hardware-based NIC such as the use of a fully customized logic based network interface can be due to the following reasons; Still it is not clear whether the General Purpose Processor (GPP) can provide the processing required for high-speed line beyond the 10 Gbps. Also, the limit of the GPP's clock in supporting the processing of network interfaces. However, using a RISC core engine for offloading the LSO function can deliver some important features to network interfaces design, such as simplicity, scalability, shorter developing cycle time. In this paper, we have investigated using a specialized RISC core to process the LSO functions for TCP/IP and UDP/IP for high-speed communications rate up to 100 Gbps. To achieve this, we have enhanced the LSO algorithm to scale it to 100 Gbps. A fast DMA is used to support transferring data in the network interface. The LSO processing methodology on the network has presented. In addition, the RISC's performance and data movements for high communication rate up to 100 Gbps have been measured. A 148 MHz RISC core can support the sending-side processing for up to 100 Gbps transmission speed for the TCP/IP and UDP/IP protocol when the MTU is applied (1500 bytes). A DMA with 3759 MHz is required to eliminate the idle cycles while transferring data over the 64-bit local bus.
Starting Page	844
Ending Page	849
File Size	166724
Page Count	6
File Format	PDF
ISBN	9781467311564
e-ISBN	9781467311571
e-ISBN	9781467311557
DOI	10.1109/ISCIT.2012.6381020
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-10-02
Publisher Place	Australia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Reduced instruction set computing Protocols RISC core Large Sending Offload (LSO) TCP/IP Nickel VHDL simulator IP networks Network interfaces Engines Clocks Cycle-accurate performance evaluations
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Design a scalable ethernet Network Interface supporting the Large Receive Offload

Large Sending Offload: Design and Implementation for High-Speed Communications Rate up to 100 Gbps

Design consideration for efficient network interface supporting the Large Receive Offload with embedded RISC

Design of FPGA based 8-bit RISC controller IP core using VHDL

TCP and UDP processing requirements for network interface design at 100 Gbps

An Evaluation of TCP and UDP Protocols Processing Required for Network Interface Design at 100 Gbps

A single clock cycle MIPS RISC processor design using VHDL

Design and evaluation of an Ethernet interface card for the Next Generation Network

A RISC core design for an ATM network interfaces

Cost effective RISC core supporting the large sending offload

Similar Documents

Design a scalable ethernet Network Interface supporting the Large Receive Offload

Large Sending Offload: Design and Implementation for High-Speed Communications Rate up to 100 Gbps

Design consideration for efficient network interface supporting the Large Receive Offload with embedded RISC

Design of FPGA based 8-bit RISC controller IP core using VHDL

TCP and UDP processing requirements for network interface design at 100 Gbps

An Evaluation of TCP and UDP Protocols Processing Required for Network Interface Design at 100 Gbps

A single clock cycle MIPS RISC processor design using VHDL

Design and evaluation of an Ethernet interface card for the Next Generation Network

A RISC core design for an ATM network interfaces

Cost effective RISC core supporting the large sending offload