NDLI: Architecture of a fault tolerant system for real time embedded applications

Content Provider	IEEE Xplore Digital Library
Author	Sinha, A. Karmakar, A. Bhattacharya, B. Bhattacharya, S. Ray, S.
Copyright Year	2002
Description	Author affiliation: R & D Center, Himachal Futuristic Commun. Ltd., India (Sinha, A.; Karmakar, A.; Bhattacharya, B.; Bhattacharya, S.; Ray, S.)
Abstract	This paper aims to present a generalized fault tolerant architecture for time critical embedded systems where microprocessors/microcontrollers are used as basic processing elements. If such a system fails at any instant of time, a standby mechanism is required to take over the responsibility of task handling automatically, without affecting the processing of the tasks. The case of a digital telephony system may be cited as an example. If such a system becomes faulty and a standby unit takes the processing responsibility instantaneously or within a maximum allowable limit of time, then no call will be dropped. The proposed architecture is based on redundancy approach and a shadow of the main memory of a unit is kept so that the standby unit can access current data and status instantly. By introducing this type of approach restoration of processing can be achieved within a short interval of time. A monitoring logic is incorporated to monitor the health of the system continuously. It is assumed that this monitoring logic will work properly even if the other portions of the system fail.
Sponsorship	IEEE Circuits & Syst. Soc. IEEE Neurla Networks Soc. Nokia Philips-Eindhoven California Inst. Telecommun. & Inf. Technol. Univ. California
Starting Page	194
Ending Page	197
File Size	721869
Page Count	4
File Format	PDF
ISBN	5742202601
DOI	10.1109/OCCSC.2002.1029078
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-06-26
Publisher Place	Russia
Access Restriction	Subscribed
Rights Holder	St. Petersburg State Poly Univ.
Subject Keyword	Real time systems Condition monitoring Microcontrollers Microprocessors Fault tolerant systems Embedded system Redundancy Telephony Logic Synchronization
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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