NDLI: Analyzing the impact of substrate noise on embedded analog-to-digital converters

Content Provider	IEEE Xplore Digital Library
Author	Zinzius, Y. Gielen, G. Sansen, W.
Copyright Year	2002
Description	Author affiliation: Dep. Elektrotechniek, Katholieke Univ., Leuven, Belgium (Zinzius, Y.; Gielen, G.; Sansen, W.)
Abstract	This paper presents the analysis and measurements of the impact of digital substrate noise on embedded Analog-to-Digital converters. The impact of substrate noise on analog design is explained, followed by a specific entire impact analysis of the impact on a regenerative comparator and an A/D converter. To confirm the analysis the substrate noise has also been measured on a test chip designed in a 0.35 /spl mu/m heavily-doped-substrate CMOS technology. From the measurements it was deduced that SNR and the effective number of bits are reduced by 20%.
Sponsorship	IEEE Circuits & Syst. Soc. IEEE Neurla Networks Soc. Nokia Philips-Eindhoven California Inst. Telecommun. & Inf. Technol. Univ. California
Starting Page	82
Ending Page	85
File Size	395786
Page Count	4
File Format	PDF
ISBN	5742202601
DOI	10.1109/OCCSC.2002.1029050
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-06-26
Publisher Place	Russia
Access Restriction	Subscribed
Rights Holder	St. Petersburg State Poly Univ.
Subject Keyword	Semiconductor device measurement Voltage CMOS technology Circuit noise Noise generators Topology Noise measurement Analog-digital conversion MOSFETs Equations
Content Type	Text
Resource Type	Article

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Analyzing the impact of substrate noise on embedded analog-to-digital converters