NDLI: Design and implementation of high-speed Reed-Solomon decoder

Content Provider	IEEE Xplore Digital Library
Author	You Yu-xin Wang Jin-xiang Lai Feng-chang Ye Yi-zheng
Copyright Year	2002
Description	Author affiliation: Microelectron. Center, Harbin Inst. of Technol., China (You Yu-xin; Wang Jin-xiang; Lai Feng-chang; Ye Yi-zheng)
Abstract	This paper presents a new VLSI design and implementation of a high-speed three-stage pipelining Reed-Solomon decoder based on the modified Euclidean algorithm. A new multiplier and inversion for GF(2/sup m/) are implemented on the composite field GF(2/sup 2n/) (m=2n), which offers lower hardware requirements compared to standard Mastrovito multiplier and ROM respectively. By setting the new initial conditions of MEA, not only decoding latency but also hardware overheads of RS (204,188) decoder is reduced greatly compared to the conventional architecture with the same decoding rate. The complexity of the proposed RS decoder is about 118,000 gates, and the decoding latency is only 220 clock cycles and has a throughput of 800 Mbit/s using 0.25 /spl mu/m CMOS process.
Sponsorship	IEEE Circuits & Syst. Soc. IEEE Neurla Networks Soc. Nokia Philips-Eindhoven California Inst. Telecommun. & Inf. Technol. Univ. California
Starting Page	146
Ending Page	149
File Size	342075
Page Count	4
File Format	PDF
ISBN	5742202601
DOI	10.1109/OCCSC.2002.1029066
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-06-26
Publisher Place	Russia
Access Restriction	Subscribed
Rights Holder	St. Petersburg State Poly Univ.
Subject Keyword	Reed-Solomon codes Algorithm design and analysis Very large scale integration Throughput Hardware Decoding Delay Read only memory Pipeline processing Clocks
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

VLSI design and implementation of high-speed RS(204,188) decoder

Implementation of high speed Reed-Solomon decoder

High-speed VLSI architecture for parallel Reed-Solomon decoder

A New High-Speed Architecture for Reed-Solomon Decoder

An ultra high-speed Reed-Solomon decoder

A VLSI design of a high-speed Reed-Solomon decoder

High-speed VLSI architecture for parallel Reed-Solomon decoder

VLSI design of Reed-Solomon decoder architectures

A single chip VLSI Reed-Solomon decoder

Design and implementation of high-speed Reed-Solomon decoder

Similar Documents

VLSI design and implementation of high-speed RS(204,188) decoder

Implementation of high speed Reed-Solomon decoder

High-speed VLSI architecture for parallel Reed-Solomon decoder

A New High-Speed Architecture for Reed-Solomon Decoder

An ultra high-speed Reed-Solomon decoder

A VLSI design of a high-speed Reed-Solomon decoder

High-speed VLSI architecture for parallel Reed-Solomon decoder

VLSI design of Reed-Solomon decoder architectures

A single chip VLSI Reed-Solomon decoder

Design and implementation of high-speed Reed-Solomon decoder