NDLI: Thermometer-to-binary decoders for flash analog-to-digital converters

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2015 European Conference on Circuit Theory and Design (ECCTD)

2013 European Conference on Circuit Theory and Design (ECCTD)

2011 20th European Conference on Circuit Theory and Design (ECCTD)

2009 European Conference on Circuit Theory and Design

2007 18th European Conference on Circuit Theory and Design

European conference on circuit theory and design 2007

ECCTD 2007 table of contents

A low-power CMOS analog voltage buffer using compact adaptive biasing

3.125 Gb/s temperature compensated CMOS optical preamplifier with automatic gain control

Low-voltage low-power 200MHz variable gain amplifier in CMOS 0.35μm

CMOS voltage feedback current amplifier

A rail-to-rail op amp for VLSI cell with constant performance

Automated synthesis of complex analog circuits

EDA for RF and analog front-ends in the 4G era: Challenges and solutions

Pareto optimization of analog circuits considering variability

An evolutionary optimization kernel using a dynamic GA-SVM model applied to analog IC design

New layout generator for analog CMOS circuits

CMOS continuous-time CMFB circuit with improved linearity

A very compact KHN filter with multidecade tuning

A 1V low power sigma-delta modulator based on floating gate MOS transistors

Class AB fully differential voltage followers

Low-voltage FGMOS-based balanced current scaling in moderate inversion

Technology-caused performance limitation of the common-gate LNA

Analysis and design of common-gate low-noise amplifier for wideband applications

Analysis of different feedback topologies to LNA input matching

A 5.3mW, 2.4GHz ESD protected Low-Noise Amplifier in a 0.13μm RFCMOS technology

A comparative study of CMOS LNAs

Practical limitations to the implementation of resistive grid filtering in Cellular Neural Networks

Implementation of an asynchronous cellular logic network as a co-processor for a general-purpose massively parallel array

Verification of Split&Shift techniques for CNN hardware reduction

Relating Cellular Non-linear Networks to Threshold Logic and Single Instruction Multiple Data computing models

High resolution analog interface for micromachined capacitive accelerometer

Design and control of a micro-cantilever tool for micro-robot contact sensing

A nanopower double-mode 1-V frequency reference for an ultra-low-power capacitive sensor interface

A low power capacitance to pulse width converter for integrated sensors

A simplified modeling approach for a MEMS capacitive sensor

LDO compensation strategy based on current buffer/amplifiers

Compensated circuit for Low Dropout Regulator having stable load regulation after consideration of bonding wire resistance

A programmable switched-capacitor relaxation oscillator with low phase jitter

Compensation method of amplitude error in sawtooth wave generator

Design of a multimode reconfigurable sigma-delta converter for 4G wireless receivers

Novel topologies of cascade ΣΔ modulators for low-voltage wideband applications

A compensation method of the excess loop delay in continuous-time complex sigma-delta modulators

Accurate and simple modeling of amplifier dc gain nonlinearity in switched-capacitor circuits

Reduction of simultaneous switching noise in analog signal band

Power supply noise and logic error probability

A switching noise vision of the optimization techniques for low-power synthesis

Effects of digital switching noise on analog circuits performance

Applications of Programmable Microwave Function Array (PROMFA)

Multiband direct RF-sampling receiver front-end for WLAN in 0.13 μm CMOS

Flexible ADCs for wireless mobile radios

A RF front-end for digital audio broadcasting

A new algorithm for high speed speech and audio coding

A study on the best wavelet filter bank problem in the wavelet-based image watermarking

Least-square-based block adaptive prediction approach for lossless image coding

A comparison between the message embedded cryptosystem and the self-synchronous stream cipher Mosquito

1V 10-bit successive approximation ADC for low power biomedical applications

An adaptive circuit for low-power sensor processing: Mismatch effects

Recent advances in the design of implantable stimulator output stages

Floating voltage-controlled current sources for electrical impedance tomography

Distortion analysis in the frequency domain of a Gm-C biquad

Linearity guidelines for gm-C biquad filter design using architecture optimization with Volterra analysis

Nonlinear on-chip capacitor characterization

A generalization of Miller formulae for nonlinear feedback networks

12-bit 2.4 GHz D/A upconverter

A two-step dynamic reference A/D converter

Analog calibration of channel mismatches in time-interleaved ADCs

Thermometer-to-binary decoders for flash analog-to-digital converters

Simultaneous estimation of gain, delay, and offset utilizing the farrow structure

An arbitrary-bandwidth transmultiplexer and its application to flexible frequency-band reallocation networks

Minimum number of operations under a general number representation for digital filter synthesis

Design of an efficient digital down-converter for a SDR-based DVB-S receiver

A broadband, inductorless LNA for multi-standard aplications

Gain-Bandwidth Limitations of 0.18μm Si-CMOS RF technology

Design optimization of staggered amplifier for wide-band applications

On the optimal design of multi-stage cascaded transistor amplifiers with noise, gain and mismatch constraints

CNN model on cell multiprocessor array

An FPGA implementation Of 2-D CNN gabor-type filter

CNN-UM based transversely isotropic elastic wave propagation simulation

Emulated digital CNN solution for two dimensional compressible flows

Design of bio-inspired network models for spatio-temporal pattern identification

Dynamics of EEG-signals in epilepsy: Spatio temporal analysis by Cellular Nonlinear Networks

Retinal prosthesis : Testing prototypes on a dystrophic rat retina

Visual homing: Experimental results on an autonomous robot

Smart, flexible, and future-proof data converters

Ultra low-power MEMS-based radio for wireless sensor networks

New highly-accurate CMOS source-degenerated based V-I converter with positive feedback

Continuous-time filter featuring Q and frequency on-chip automatic tuning

A CMOS fifth-order 400MHz current-mode LF linear phase filter for hard disk read channels

Design optimization of wave active filters

LMS-based calibration of pipelined ADCs including linear and nonlinear errors

Methodology for mismatch reduction in time-interleaved ADCs

Design of a 1.8V 8-bit 500MSPS folding-interpolation CMOS A/D converter with a folder averaging technique

Analyzing the performance degradation of flash A/D converters due to substrate noise coupling

A high-speed hardware implementation of the Hermes8-128 stream cipher

A general model of DPA attacks to precharged busses in symmetric-key cryptographic algorithms

Arithmetic and architectural design to reduce leakage in nano-scale digital circuits

Current sensing completion detection for subthreshold asynchronous circuits

OOK/NCP-FSK modulator based on coupled open-closed-loop VCOs

T1/E1/J1 receiver in CMOS

Envelope tracking power amplifier with static predistortion linearization

Fundamental blocks of single ended LVCMOS output buffer- a circuit level design guideline

Clocking and WTA design of a continuous time Hopfield net with parasitic capacitances

A realization of FIR system characterizing outline of fingers and its application to person identification

Improved fast encoding method of vector quantization based on dynamic element reordering for codewords

Improvement of watermark detection process based on Bayesian estimation

Bioimpedance monitoring with improved accuracy using three-level stimulus

Analysis of an adaptive algorithm for feedback cancellation in hearing aids for sinusoidal signals

EEG signal compression based on Classified Signature and Envelope Vector Sets

Discrimination between human functional ability/disability by means of different classification methodologies

First-order allpass sections-based high-input low output impedance voltage-mode universal filter using FDCCIIs

SI-biquad based on direct-form digital filters

Single-stage CMOS OTA for active-RC filter design

CCII-based high-valued inductance simulators with minumum number of active elements

Theoretical and practical minimum of the power Consumption of 3 ADCs in SC technique

Current-mode circuits for sigma-delta converters

Design procedure for optimizing the power consumption of two-stage Miller compensated amplifiers in SC circuits

A sample-and-hold circuit with very low gain error for time interleaving applications

A low-power high-radix serial-parallel multiplier

Design of fixed-width multipliers with minimum mean square error

High speed galois fields $GF(2^{m})$ multipliers

VHDL implementation of fast NxN multiplier based on vedic mathematic

Implementation of generalized uniform Bandpass Sampling with complex FIR and IIR Filtering

Reconfigurable digital Delta-Sigma Modulator Synthesis for digital wireless transmitters

A design of multi-GHz continuous-time bandpass filters using 0.1-μm HEMT technology

Power amplifiers linearization based on digital predistortion with memory effects used in CDMA applications

An automatic tool to design CNN-UM programs

Vision based human-machine interface via hand gestures

A CNN-based algorithm for moving object detection in stereovision applications

On the digital simulation of linear cellular neural networks

An adaptive multi-resolution algorithm for motion estimation in medical image sequences

On chip implementation of a pixel-parallel approach for retinal vessel tree extraction

Locating and reading color displays with the bionic eyeglass

FPGA implementation of 3D discrete wavelet transform for real-time medical imaging

Low quiescent current high speed amplifier for LCD column driver

A rail-to-rail DC-enhanced adaptive biased fully differential OTA

Low voltage gain boosting schemes for one stage operational amplifiers

Sub-1V CMOS OTA with body-driven gain boosting

CMOS Miller OTA with body-biased output stage

Combined simplex-trust-region optimization algorithm for automated IC design

Clustering algorithms for circuit partitioning and placement problems

Switched-current filter optimization based on evolutionary algorithms

Designing VFs by applying genetic algorithms from nullator-based descriptions

Automated cost function formulation for analog design optimization

Optimal dithered digital sigma-delta modulators for fractional-N frequency synthesizers

A novel dual-loop multi-phase frequency synthesizer

Optimizing the design of an injection-locked frequency divider by means of nonlinear analysis

A new method for the determination of the locking range of oscillators

A circular voltage-controlled phase shifter with unlimited phase range for phase tracking loops

Derivation of power amplifier predistortion circuits by frequency to signal amplitude transformation

Split-band supply modulator for OFDM polar transmitter: Filter design

Feedthrough cancellation in a class E amplified polar transmitter

Ultra-low power 2.4 GHz CMOS receiver front-end for sensor nodes

Improving the quality factor estimation for differentially driven RF CMOS inductor

A switching mode power supply with digital pulse density modulation control

Linear-assisted converter with constant switching frequency

Modeling of linear-assisted DC-DC converters

A discussion on exponential-gain charge pump

Impact of control signal skews on self-boosted charge pumps

Digital post-processing for testable random bit generators

Second-level testing revisited and applications to NIST SP800-22

A study on random bit generators with post-processing by shift registers and modulo-2 addition

On the convergence to regime of ADC-based true random number generators

On the generation of pseudo-random sequences exploiting digitized chaotic systems

Single Miller capacitor frequency compensation with nulling resistor for three-stage amplifiers

Mismatch tolerant, continuous time, rail to rail, gain enhanced CMOS amplifiers

Power-constrained bandwidth optimization in cascaded open-loop amplifiers

Design methodology of nested-Miller amplifiers for small capacitive loads

Transmission line modelling using wave equation standing-wave solutions as basis functions

A new approach to analysis and simulation of single and coupled low-loss interconnects.

Highly-accurate propagation delay analytical model of an RC-circuit with a ramp input

Models for the LE-FDTD resistive voltage source spanning multiple cells

A design methodology for low-power MCML ring oscillators

Sorter-based sigma-delta domain arithmetic circuits

Piecewise linear circuits operating on first-order multi-level and second-order binary sigma-delta modulated signals

Code compression for ARM7 embedded systems

Analytical calculation of BER in communication systems using a piecewise linear chaotic map

The ultimate capacity of MIMO channels and its realization

Low cost error recovery in Delay-Intolerant Wireless Sensor Networks

Efficient construction and implementation of short LDPC codes for wireless sensor networks

Using high pass sigma-delta modulation for Class-S power amplifiers

An efficient parallel structure for ΣΔ modulators for use in high speed switching power amplifiers

Derivation of the sliding domain for a buck-based switching amplifier in wideband signal tracking applications

Using Taylor predictor to improve stabilization of steady state in third-order chaotic system

Multi-user detection for an asynchronous differential chaos-based multiple access system

Study of discretization of two-dimensional sliding mode control systems

Limit cycles in Digital Bang-Bang PLLs

Nonlinearities: Your worst enemies…? … Your best friends!

A highly linear low voltage CMOS triode transconductor

Very low voltage CMOS two-stage amplifier

A low-power multilevel-output classifier circuit

A low-voltage, low-power, high-linearity cmos four-quadrant analog multiplier

Improved Analytical I-V model for polygonal-shape enclosed layout transistors

An algorithm for battery modeling and life time maximization of small size electric systems

Improved noise wave model of microwave FETs based on artificial neural networks

Multiple adaptive neuro-fuzzy inference systems for accurate microwave CAD applications

Energy consumption in RLC tree circuits

A fast transient simulation based on Model Order Reduction and RLCG-MNA formulation

Automated diagnostic system using graph clustering algorithm and fuzzy logic method

On reconstruction of conductances in resistor grids from boundary measurements

Efficient CMOS driver-receiver pair with low-swing signaling for on-chip interconnects

Low-power single-ended I/O circuit for binary interchip communications

High performance bootstrapped CMOS low to high-swing level-converter for on-chip interconnects

Very high-speed carry computation based on mixed dynamic/transmission-gate Full Adders

Global robust stability of bidirectional associative memory neural networks

Obtaining decision boundaries of CSFNN neurons using current mode analog circuitry

Scale-rule selection of affordable neural network for chaotic time series learning

Optimized cellular neural network universal machine emulation on FPGA

Influence of topology on synchronization in networks of coupled Hindmarsh-Rose neurons

Clustering phenomenon of chaotic circuits coupled symmetrically by mutual inductors

CMOS circuit implementation of a coupled phase oscillator system using pulse modulation approach

Analysis of synchronization phenomena in star-coupled Wien-bridge oscillators using distorted waves

A method for multiple fault diagnosis in dynamic analogue circuits

A common-sense based approach to the automated test-point selection in fault diagnosis

Polynomial fault diagnosis of linear analog circuits

Design and development of a versatile testing system for analog and mixed-signal circuits

Synthesis of threshold logic circuits using tree matching

Behavioral models of basic mixed-mode circuits: practical issues and application

Road map representation of s-expanded symbolic network functions

Bluetooth Baseband power analysis with PKtool

A path searching method based on circuit analysis for nonlinear resistive networks

Absolute stability of single variable Lur’e systems

FPGA implementation of a new scheme for the circuit realization of PWL functions

PWL approximation of the Hindmarsh-Rose neuron model in view of its circuit implementation

A small chip area 12-b 300MS/s Current Steering CMOS D/A converter based on a laminated-step layout technique

Simulation of quadrature-bandpass Sigma-Delta analog to digital converters using state space descriptions

Comparison of active and passive mixers

Design and implementation of a miniaturised, low power wireless sensor node

Topological conditions for passive switches in switching converters

A Matlab tool for analysis of switch-mode power supplies

The minimum energetical principle in electric and magnetic circuits

Analog circuits for thermistor linearization with Chebyshev-optimal linearity error

Closed-Form expression of frequency pulling in unlocked-driven nonlinear oscillators

Harmonic balance, Melnikov method and nonlinear oscillators under resonant perturbation

Breakdown of synchronization in chaotic oscillators and noisy oscillators

An IC implementation of a hysteresis two-port VCCS chaotic oscillator

Correct operation in SMOBILE-based quasi-differential quantizers

Single electron transistor based chua type chaotic circuit: A SPICE assisted proof

Pipelined array multiplier based on quantum-dot cellular automata

Assessing quantum circuits reliability with mutant-based simulated fault injection

SOI pixel detector based on CMOS time-compression charge-injection

A collision-free time-to-first spike camera architecture based on a winner-take-all network

3D integrated scalable focal-plane processor array

A readout system for inductive position sensors

AN electrical equivalent circuit model For RF MEMS disk resonators

FFinder: A MAPLE-based CAD frame for identifying feedback loops in electric circuits

Symbolic hybrid analysis of nonlinear analog circuits

Systematic equation formulation

Applying an iterative-decomposed piecewise-linear model to find multiple operating points

Finding all the DC solutions of transistor circuits with the thermal constraint

Noise cancellation and noise minimization techniques for low cost compact size configurable RF oscillators/VCOs

Wideband 0.18μm CMOS VCO using active inductor with negative resistance

Large-signal analysis of CMOS - LC VCOs

Self-injection locked compact coupled planar resoator based cost-effective ultra low phase noise VCOs For wireless systems

A numerical technique for time domain noise analysis of oscillators

Analysis of switching effects in DC-DC converters via bias point computation

Classification of parallel DC/DC converters part I: circuit theory

Classification of parallel DC/DC converters part II: Comparisons and experimental verifications

Ripple-based Period-2 bifurcation border detection in switching power regulators

Four-quadrant switch-mode gyrator

High frequency chaos oscillators with applications

Chaotic dynamics of the fractional Chua’s circuit: Time-domain analysis via decomposition method

The bifurcation behaviour of a novel second order model of the Hodgkin-Huxley Neuron

Some more robustness conditions for the invariant density of a class of 1D maps under additive noise

ECCTD author index

Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.

Thermometer-to-binary decoders for flash analog-to-digital converters

Content Provider	IEEE Xplore Digital Library
Author	Sail, E. Vesterbacka, M.
Copyright Year	2007
Description	Author affiliation: Dept. of Electr. Eng., Linkoping Univ., Linkoping (Sail, E.; Vesterbacka, M.)
Abstract	Decoders for low power, high-speed flash ADCs are investigated. The sensitivity to bubble errors of the ROM decoder with error correction, ones-counter, 4-level folded Wallace-tree, and multiplexer-based decoder are simulated. The ones-counter and multiplexer-based decoder, corresponding to the error insensitive and hardware efficient cases, are implemented in a 130 nm CMOS SOI technology. Measurements yield an ENOB of about 4.1 bit for both, and energy consumption of 80 pJ and 60 pJ, for the respective decoders. Hence we conclude that the MUX-based decoder seems to be a good choice with respect to area, efficiency, and speed.
Starting Page	240
Ending Page	243
File Size	151317
Page Count	4
File Format	PDF
ISBN	9781424413416
DOI	10.1109/ECCTD.2007.4529581
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-08-27
Publisher Place	Spain
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Silicon on insulator technology Energy consumption Circuits CMOS technology Sampling methods Decoding Error correction Analog-digital conversion Read only memory Propagation delay
Content Type	Text
Resource Type	Article

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