NDLI: A novel ROM architecture for reducing bubble and metastability errors in high speed flash ADCs

Content Provider	IEEE Xplore Digital Library
Author	Rahman, M. Baishnab, K.L. Talukdar, F.A.
Copyright Year	2010
Description	Author affiliation: Dept. of Electronics & Communication Engg., National Institute of Technology Silchar, Assam, PIN-788010, India (Rahman, M.; Baishnab, K.L.; Talukdar, F.A.)
Abstract	In a flash ADC, output of the comparators constitute the thermometer code. This thermometer code is converted to binary code with the help of a thermometer to binary decoder using a ROM. However, this conversion scheme suffers from metastability and bubble errors. A novel ROM architecture has been proposed which suppresses metastability, both first and second order bubble errors. It eliminates the need of an error correction circuit in the front end of the ROM thereby reducing power consumption, area requirement and removing the delay associated with the additional stage. This architecture also eliminates the need of Gray coded ROM and Gray to binary converter thereby making the circuit simpler.
Starting Page	15
Ending Page	19
File Size	594109
Page Count	5
File Format	PDF
ISBN	9781424453528
DOI	10.1109/CONIELECOMP.2010.5440805
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-02-22
Publisher Place	Mexico
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Read only memory Metastasis Error correction Decoding Circuits Binary codes Voltage Delay Sampling methods Energy consumption metastability error CMOS memory circuits analog digital conversion digital error correction bubble error
Content Type	Text
Resource Type	Article

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