NDLI: Efficient CMOS driver-receiver pair with low-swing signaling for on-chip interconnects

Content Provider	IEEE Xplore Digital Library
Author	Garcia, J.C. Montiel-Nelson, J.A. Nooshabadi, S.
Copyright Year	2007
Description	Author affiliation: Inst. for Appl. Microelectron., Univ. of Las Palmas de Gran Canaria, Las Palmas (Garcia, J.C.; Montiel-Nelson, J.A.)
Abstract	This paper describes the design of a symmetric low-swing driver-receiver pair (mj-sib) for driving signals on the global interconnect lines. When implemented on a 0.13 mum CMOS 1.2 V technology, mj-sib scheme reduces energy-delay product by 41.7% (at the receiver load of 0.25 pF) and has 38.8% lower delay when compared with a counterpart asymmetric low-swing signaling scheme. Also, mj-sib topology has 14.2% lower energy-delay product and has 36% lower active area (50.25 $mum^{2})$ when compared with other symmetric low-swing signaling structure. The key advantages of the proposed signaling scheme is that it requires only one power supply and threshold voltage, hence significantly reducing the design complexity.
Starting Page	787
Ending Page	790
File Size	130933
Page Count	4
File Format	PDF
ISBN	9781424413416
DOI	10.1109/ECCTD.2007.4529714
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-08-27
Publisher Place	Spain
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Power supplies Wires Integrated circuit interconnections CMOS technology Threshold voltage Power dissipation Diodes Signal design MOSFETs Driver circuits
Content Type	Text
Resource Type	Article

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