NDLI: A New Method to Reduce the Side-Channel Leakage Caused by Unbalanced Capacitances of Differential Interconnections in Dual-Rail Logic Styles

Content Provider	IEEE Xplore Digital Library
Author	Jianping Quan Guoqiang Bai
Copyright Year	2009
Abstract	Recently DPA resistant logic styles are of great concern. As far as we know, each kind of logic style has its own drawbacks. Masking logic styles can easily be attacked by the template attack. For dual-rail logic styles, TDPL can only keep the total power consumption of the whole cycle constant; as for WDDL, it becomes more and more difficult to efficiently match the interconnect capacitances of differential wires with shrinking feature sizes. To avoid these drawbacks, we present a new direction for routing effort to solve the unbalanced interconnection problem. By using Three-phase logic and removing the load dependent power consumption in the evaluation phase and discharge phase, our logic style is insensitive to the unbalanced interconnect capacitances of differential wires. Additionally, the early propagation effect is another threat to certain DPA resistant logic styles. We also propose a theoretical method to solve it at the system level.
Starting Page	58
Ending Page	63
File Size	357191
Page Count	6
File Format	PDF
ISBN	9781424437702
DOI	10.1109/ITNG.2009.185
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-04-27
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Energy consumption Routing Microelectronics early propagation effect TDPL Information technology routing Power measurement Wires Power system interconnection NSDDL unbalanced interconnections Capacitance Logic WDDL Clocks
Content Type	Text
Resource Type	Article

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