NDLI: A modular synchronizing FIFO for NoCs

Content Provider	IEEE Xplore Digital Library
Author	Ono, T. Greenstreet, M.
Copyright Year	2009
Description	Author affiliation: Sun Microsystems, USA (Ono, T.) \|\| University of British Columbia, Canada (Greenstreet, M.)
Abstract	Systems-on-chip designs often use functional blocks operating at different clock frequencies. This motivates the use of an asynchronous network-on-chip (NoC) with synchronizing FIFOs interfacing between the NoC and the functional blocks. To minimize design time, these FIFOs should be constructed from cells available in a standard cell library and configurable to work in a wide range of applications. We present a modular synchronizing FIFO design that can be implemented using logic gates from a typical standard-cell library. The FIFO has interchangeable input and output interfaces for edge-triggered synchronous communication and for two asynchronous handshake protocols: asP* and LEDR. The FIFO capacity, synchronizer latency and interface protocols are independent parameters, allowing the FIFO to be easily configured for different NoC requirements. We evaluate performance using post-layout simulation results and analyze the metastability induced failure rate for synchronization latencies from half a clock cycle up to three clock cycles.
Starting Page	224
Ending Page	233
File Size	452510
Page Count	10
File Format	PDF
ISBN	9781424441426
DOI	10.1109/NOCS.2009.5071471
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-05-10
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Analytical models Protocols Network-on-a-chip Logic gates Application specific processors Libraries Logic design Frequency synchronization Delay Clocks
Content Type	Text
Resource Type	Article

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